Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58220 )
Change subject: soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR ......................................................................
soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR
Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only.
Change-Id: Ia196906d3c2636742ae90160a224354e8df7863a Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/58220 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@mailbox.org Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/cannonlake/cpu.c 1 file changed, 2 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 821694e..99fcadd 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -62,8 +62,9 @@ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); if (cfg->max_package_c_state && (msr.lo & 0xf) >= cfg->max_package_c_state) { msr.lo = (msr.lo & ~0xf) | ((cfg->max_package_c_state - 1) & 0xf); - wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); } + msr.lo |= CST_CFG_LOCK_MASK; + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* C-state Interrupt Response Latency Control 0 - package C3 latency */ msr.hi = 0;