[coreboot-gerrit] Change in coreboot[master]: soc/skylake: lock aesni msr

[Michael Niewöhner (Code Review)]

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock aesni msr
......................................................................

soc/skylake: lock aesni msr

Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521
Signed-off-by: Michael Niewöhner 
---
M src/soc/intel/skylake/cpu.c
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/1

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 0d49d28..984c134 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -420,6 +420,16 @@
    wrmsr(MSR_EMULATE_PM_TIMER, msr);
 }

+void cpu_lock_aesni(void) {
+	msr_t msr;
+
+	msr = rdmsr(MSR_FEATURE_CONFIG);
+	if ((msr.lo & 1) == 0) {
+		msr.lo |= 1; /* Lock it */
+		wrmsr(MSR_FEATURE_CONFIG, msr);
+	}
+}
+	
 /* All CPUs including BSP will run the following function. */
 void soc_core_init(struct device *cpu)
 {
@@ -442,6 +452,9 @@
    /* Configure Intel Speed Shift */
    configure_isst();

+	/* Lock AES-NI MSR */
+	cpu_lock_aesni();
+
    /* Enable ACPI Timer Emulation via MSR 0x121 */
    enable_pm_timer_emulation();