Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Edward O'Callaghan, Sridhar Siricilla, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44645
to look at the new patch set (#5).
Change subject: mb/google/dedede: Enable CSE Board Reset Override ......................................................................
mb/google/dedede: Enable CSE Board Reset Override
This will ensure that the cold reset is performed when CSE Lite jumps from RO to RW.
BUG=b:162386991 TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP. On board with cr50 firmware version 0.0.22: =========================================== coreboot-coreboot-unknown.9999.6fcde00 Fri Aug 21 05:12:01 UTC 2020 ramstage starting (log level: 8)... <snip> cse_lite: RO version = 13.50.0.7130 (Status=0x0, Start=0x1000, End=0xeafff) cse_lite: RW version = 13.50.0.7130 (Status=0x0, Start=0xeb000, End=0x26afff) <snip> cse_lite: Set Boot Partition Info Command (RW) Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.0.22/cr50_v1.1.6138-b9f0b1d Initialized TPM device CR50 revision 0
coreboot-coreboot-unknown.9999.6fcde00 Fri Aug 21 05:12:01 UTC 2020 bootblock starting (log level: 8)... CPU: Genuine Intel(R) CPU 0000 @ 1.10GHz <snip>
On board with cr50 firmware version 0.6.5: ========================================== coreboot-coreboot-unknown.9999.6fcde00 Fri Aug 21 05:12:01 UTC 2020 ramstage starting (log level: 8)... <snip> cse_lite: RO version = 13.50.0.7130 (Status=0x0, Start=0x1000, End=0xeafff) cse_lite: RW version = 13.50.0.7130 (Status=0x0, Start=0xeb000, End=0x26afff) <snip> cse_lite: Set Boot Partition Info Command (RW) Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.5/cr50_v1.9308_B.889-3dad44541 Initialized TPM device CR50 revision 0 Cr50 firmware does not use SYS_RESET#, version: 0.6.5 HECI: Global Reset(Type:1) Command
coreboot-coreboot-unknown.9999.6fcde00 Fri Aug 21 05:12:01 UTC 2020 bootblock starting (log level: 8)... CPU: Genuine Intel(R) CPU 0000 @ 1.10GHz <snip>
Change-Id: I46a390c71e380328cd7fe70214df09553b2db75c Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/mainboard.c 2 files changed, 1 insertion(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44645/5