Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83948?usp=email )
Change subject: soc/intel/common/block/cpu: Fix ways count computation regression ......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83948/comment/f3cc5473_d9cefab0?usp... : PS11, Line 32: TEST=Verified on PTL Intel reference platform
For the ignorant, how can this be verified?
I performed the following experiment:
On Panther Lake, I set `DCACHE_RAM_SIZE` to `0x400000` (4 MB). Without the patches the number of ways on a 18 MB is going to be `0x400000 / 0x180000` = 2.66 = 3. While actually according the specification (EDS / HAS), we should only consider the biggest number of two of the way size and the computation should be `0x400000 / 0x100000` = 4.
It boots just fine with this patch but it crashes with page fault exception if I unselect `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE`.