Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian, Mark Hasemeyer.
Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 )
Change subject: mb/google/myst: Enable PCIe devices in devicetree ......................................................................
Patch Set 31:
(6 comments)
File src/mainboard/google/myst/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74112/comment/b002f3f3_fb00a5f2 PS31, Line 12: .start_logical_lane = 13, : .end_logical_lane = 13, https://ee-schematics.teams.x20web.corp.google.com/myst/myst/proto0/referenc...
PCIe GPP 12
https://review.coreboot.org/c/coreboot/+/74112/comment/95b9e240_030a0189 PS31, Line 18: .link_aspm = ASPM_L1, : .link_aspm_L1_1 = true, : .link_aspm_L1_2 = true, Considering all of the trouble we've had with ASPM in the past, I would suggest disabling it for all of these and marking them with a TODO to re-enable it once we can boot/suspend/resume without issues.
https://review.coreboot.org/c/coreboot/+/74112/comment/627951c9_d5cc8deb PS31, Line 44: GEN3 GEN1
https://review.coreboot.org/c/coreboot/+/74112/comment/fe75c5cb_197b6dcd PS31, Line 59: GEN3 GEN4
https://review.coreboot.org/c/coreboot/+/74112/comment/07b529f5_866c0a6c PS31, Line 101: *dxio_descs = myst_phx_dxio_descriptors; : *dxio_num = ARRAY_SIZE(myst_phx_dxio_descriptors); : *ddi_descs = myst_phx_ddi_descriptors; : *ddi_num = ARRAY_SIZE(myst_phx_ddi_descriptors); Are these values actually specific to Phoenix?
If so, can we validate the SOC we're running on before applying them, and add a TODO for HP1/2? Otherwise, this feels like a bit of a silent trap that's easy to be missed when trying to bring up the new SOCs.
However, if they're expected to keep working, the `phx` should be dropped from the name to avoid confusion.
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74112/comment/c0b32723_ce38a219 PS8, Line 52: device ref gpp_bridge_2_4 on end # NVMe
My lane mapping in port_descriptors was incorrect, but these are notional naming conventions and can […]
We need to make sure the naming is updated in depthcharge also:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+...