Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9254
-gerrit
commit 3977e55646c43e202c7a52a13a3b82515dd1754e Author: Julius Werner jwerner@chromium.org Date: Mon Oct 6 13:41:28 2014 -0700
veyron_pinky/rk3288: Use KHz, MHz and GHz constants
Use the previously added frequency constants.
BUG=None TEST=Compiled Veyron_Pinky.
Original-Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0 Original-Signed-off-by: Julius Werner jwerner@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/221800 Original-Reviewed-by: David Hendricks dhendrix@chromium.org
(cherry picked from commit 41bb8026818b4381d4a6d43d2d433c207c3971bc) Signed-off-by: Aaron Durbin adurbin@chromium.org
Change-Id: I37a610d57f1a3d44796bf80de5104c2b5b3f3dac --- src/mainboard/google/veyron_pinky/bootblock.c | 4 +-- .../sdram_inf/sdram-ddr3-hynix-2GB.inc | 2 +- .../sdram_inf/sdram-ddr3-samsung-2GB.inc | 2 +- .../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 2 +- src/soc/rockchip/rk3288/clock.c | 15 +++++----- src/soc/rockchip/rk3288/clock.h | 18 ++++++------ src/soc/rockchip/rk3288/sdram.c | 32 +++++++++++----------- src/soc/rockchip/rk3288/spi.c | 2 +- src/soc/rockchip/rk3288/timer.c | 1 - src/soc/rockchip/rk3288/timer.h | 5 ++-- 10 files changed, 41 insertions(+), 42 deletions(-)
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index d4f82de..3ed8e27 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -32,11 +32,11 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11000000); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
/* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9000000); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc index 409a7ca..07161c0 100644 --- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ .noc_timing = 0x2891E41D, .noc_activate = 0x5B6, .ddrconfig = 3, - .ddr_freq = 533000000, + .ddr_freq = 533*MHz, .dramtype = DDR3, .num_channels = 2, .stride = 9, diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc index 3fdbecf..f5793d1 100644 --- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc @@ -70,7 +70,7 @@ .noc_timing = 0x30B25564, .noc_activate = 0x627, .ddrconfig = 3, - .ddr_freq = 666000000, + .ddr_freq = 666*MHz, .dramtype = DDR3, .num_channels = 2, .stride = 9, diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc index 315e542..f42f1b1 100644 --- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -70,7 +70,7 @@ .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, .ddrconfig = 2, - .ddr_freq = 533000000, + .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, .stride = 9, diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 8202ef2..0ce3f94 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -65,8 +65,8 @@ check_member(rk3288_cru_reg, cru_emmc_con[1], 0x021c); static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE;
#define PLL_DIVISORS(hz, _nr, _no) {\ - .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / 24000000), .no = _no};\ - _Static_assert(((u64)hz * _nr * _no / 24000000) * 24000000 /\ + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / (24*MHz)), .no = _no};\ + _Static_assert(((u64)hz * _nr * _no / (24*MHz)) * (24*MHz) /\ (_nr * _no) == hz,\ #hz "Hz cannot be hit with PLL divisors in " __FILE__);
@@ -337,10 +337,10 @@ void rkclk_configure_ddr(unsigned int hz) { struct pll_div dpll_cfg;
- if (hz <= 150000000) { + if (hz <= 150*MHz) { dpll_cfg.nr = 3; dpll_cfg.no = 8; - } else if (hz <= 540000000) { + } else if (hz <= 540*MHz) { dpll_cfg.nr = 6; dpll_cfg.no = 4; } else { @@ -348,10 +348,9 @@ void rkclk_configure_ddr(unsigned int hz) dpll_cfg.no = 1; }
- dpll_cfg.nf = (hz / 1000 * dpll_cfg.nr * dpll_cfg.no) / 24000; - assert(dpll_cfg.nf < 4096 - && hz == dpll_cfg.nf * 24000 / (dpll_cfg.nr * dpll_cfg.no) - * 1000); + dpll_cfg.nf = (hz/KHz * dpll_cfg.nr * dpll_cfg.no) / (24*KHz); + assert(dpll_cfg.nf < 4096 && hz == dpll_cfg.nf * (24*KHz) / + (dpll_cfg.nr * dpll_cfg.no) * 1000); /* pll enter slow-mode */ writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW), &cru_ptr->cru_mode_con); diff --git a/src/soc/rockchip/rk3288/clock.h b/src/soc/rockchip/rk3288/clock.h index b206baa..7a1dba0 100644 --- a/src/soc/rockchip/rk3288/clock.h +++ b/src/soc/rockchip/rk3288/clock.h @@ -22,17 +22,17 @@
#include "addressmap.h"
-#define APLL_HZ 816000000 -#define GPLL_HZ 594000000 -#define CPLL_HZ 384000000 +#define APLL_HZ (816*MHz) +#define GPLL_HZ (594*MHz) +#define CPLL_HZ (384*MHz)
-#define PD_BUS_ACLK_HZ 148500000 -#define PD_BUS_HCLK_HZ 148500000 -#define PD_BUS_PCLK_HZ 74250000 +#define PD_BUS_ACLK_HZ (148500*KHz) +#define PD_BUS_HCLK_HZ (148500*KHz) +#define PD_BUS_PCLK_HZ (74250*KHz)
-#define PERI_ACLK_HZ 148500000 -#define PERI_HCLK_HZ 148500000 -#define PERI_PCLK_HZ 74250000 +#define PERI_ACLK_HZ (148500*KHz) +#define PERI_HCLK_HZ (148500*KHz) +#define PERI_PCLK_HZ (74250*KHz)
void rkclk_init(void); void rkclk_configure_spi(unsigned int bus, unsigned int hz); diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 6c0c7fd..2b0a396 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -538,8 +538,8 @@ static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs, u32 freq) { int i; - if (freq <= 250000000) { - if (freq <= 150000000) + if (freq <= 250*MHz) { + if (freq <= 150*MHz) clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); else setbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); @@ -651,19 +651,19 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) writel(sdram_params->noc_activate, &msch_regs->activate); writel(BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1), &msch_regs->devtodev); - writel(PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / 1000000 - * 5120, 1000)) - | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / 1000000 - * 50, 1000)) + writel(PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq/MHz + * 5120, 1000)) + | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq/MHz + * 50, 1000)) | PRT_ITMSRST(8), &ddr_publ_regs->ptr[0]); - writel(PRT_DINIT0(div_round_up(sdram_params->ddr_freq / 1000000 - * 500000, 1000)) - | PRT_DINIT1(div_round_up(sdram_params->ddr_freq / 1000000 - * 400, 1000)), &ddr_publ_regs->ptr[1]); - writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq / 1000000 - * 200000, 1000)) - | PRT_DINIT3(div_round_up(sdram_params->ddr_freq / 1000000 - * 1000, 1000)), &ddr_publ_regs->ptr[2]); + writel(PRT_DINIT0(div_round_up(sdram_params->ddr_freq/MHz + * 500000, 1000)) + | PRT_DINIT1(div_round_up(sdram_params->ddr_freq/MHz + * 400, 1000)), &ddr_publ_regs->ptr[1]); + writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq/MHz + * 200000, 1000)) + | PRT_DINIT3(div_round_up(sdram_params->ddr_freq/MHz + * 1000, 1000)), &ddr_publ_regs->ptr[2]);
switch (sdram_params->dramtype) { case LPDDR3: @@ -971,9 +971,9 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) printk(BIOS_INFO, "Starting SDRAM initialization...\n");
if ((sdram_params->dramtype == DDR3 - && sdram_params->ddr_freq > 800000000) + && sdram_params->ddr_freq > 800*MHz) || (sdram_params->dramtype == LPDDR3 - && sdram_params->ddr_freq > 533000000)) + && sdram_params->ddr_freq > 533*MHz)) die("SDRAM frequency is to high!");
rkclk_configure_ddr(sdram_params->ddr_freq); diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index 431b2d3..a74d423 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -36,7 +36,7 @@ struct rockchip_spi_slave { };
#define SPI_TIMEOUT_US 1000 -#define SPI_SRCCLK_HZ 99000000 +#define SPI_SRCCLK_HZ (99*MHz) #define SPI_FIFO_DEPTH 32
static struct rockchip_spi_slave rockchip_spi_slaves[3] = { diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c index 3a2c34d..91186cc 100644 --- a/src/soc/rockchip/rk3288/timer.c +++ b/src/soc/rockchip/rk3288/timer.c @@ -18,7 +18,6 @@ */
#include <console/console.h> -#include <timer.h> #include <delay.h> #include <arch/io.h> #include "timer.h" diff --git a/src/soc/rockchip/rk3288/timer.h b/src/soc/rockchip/rk3288/timer.h index 1820f56..9f1fbaf 100644 --- a/src/soc/rockchip/rk3288/timer.h +++ b/src/soc/rockchip/rk3288/timer.h @@ -21,10 +21,11 @@ #define __SOC_ROCKCHIP_RK3288_TIMER_H__
#include <inttypes.h> +#include <timer.h> #include "addressmap.h"
-#define SYS_CLK_FREQ 24000000 -static const u32 clocks_per_usec = SYS_CLK_FREQ/1000000; +#define SYS_CLK_FREQ (24*MHz) +static const u32 clocks_per_usec = SYS_CLK_FREQ/USECS_PER_SEC;
struct rk3288_timer { u32 timer_load_count0;