Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu.
Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83928?usp=email )
Change subject: soc/mediatek/mt8196: Fix timer reset in BL31 ......................................................................
soc/mediatek/mt8196: Fix timer reset in BL31
1. Set systimer compensation to version 2.0. 2. The system does not need to serve pending IRQ from systimer after rebooting. Therefore we clear systimer IRQ pending bit at early booting.
TEST=Build pass and timestamp is not reset in ATF and payload BUG=b:343881008
Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59 Signed-off-by: Zhanzhan Ge zhanzhan.ge@mediatek.corp-partner.google.com --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/timer.h M src/soc/mediatek/mt8196/timer.c A src/soc/mediatek/mt8196/timer_prepare.c 4 files changed, 62 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/83928/1
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index c63de51..5fd5113 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -6,7 +6,7 @@ all-y += ../common/gpio.c ../common/gpio_op.c gpio.c all-$(CONFIG_SPI_FLASH) += spi.c all-y += ../common/i2c.c i2c.c -all-y += timer.c +all-y += timer.c timer_prepare.c all-y += ../common/uart.c
bootblock-y += bootblock.c diff --git a/src/soc/mediatek/mt8196/include/soc/timer.h b/src/soc/mediatek/mt8196/include/soc/timer.h index d6422c5..eeaf8ad 100644 --- a/src/soc/mediatek/mt8196/include/soc/timer.h +++ b/src/soc/mediatek/mt8196/include/soc/timer.h @@ -2,12 +2,36 @@
/* * This file is created based on MT8196 Functional Specification - * Chapter number: 5.13 + * Chapter number: 1.2 2.2 */
#ifndef SOC_MEDIATEK_MT8196_TIMER_H #define SOC_MEDIATEK_MT8196_TIMER_H
+#include <soc/addressmap.h> #include <soc/timer_v2.h> +#include <stdint.h> + +#define SYST_CON_EN BIT(0) +#define SYST_CON_IRQ_CLR BIT(4) +#define REV_CLR BIT(17) +#define REV_EN BIT(18) +#define SYSTIMER_CNT 8 + +struct systimer { + u32 cntcr; /* 0x0*/ + u32 reserved; + u32 cntcv_l; /* 0x8*/ + u32 cntcv_h; /* 0xC*/ + u32 reserved1[0x30]; + struct { + u32 con; + u32 val; + } cnttval[SYSTIMER_CNT]; +}; + +check_member(systimer, cntcr, 0x0); +check_member(systimer, cntcv_l, 0x0008); +check_member(systimer, cntcv_h, 0x000c);
#endif diff --git a/src/soc/mediatek/mt8196/timer.c b/src/soc/mediatek/mt8196/timer.c index 9d8dd7a..bf3f3ce 100644 --- a/src/soc/mediatek/mt8196/timer.c +++ b/src/soc/mediatek/mt8196/timer.c @@ -3,8 +3,11 @@ #include <arch/lib_helpers.h> #include <commonlib/helpers.h> #include <delay.h> +#include <soc/timer.h>
void init_timer(void) { - raw_write_cntfrq_el0(13 * MHz); + timer_prepare(); + + raw_write_cntfrq_el0(GPT_MHZ * MHz); } diff --git a/src/soc/mediatek/mt8196/timer_prepare.c b/src/soc/mediatek/mt8196/timer_prepare.c new file mode 100644 index 0000000..4d2c7d6 --- /dev/null +++ b/src/soc/mediatek/mt8196/timer_prepare.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 1.2 2.2 + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/timer.h> + +static void clear_systimer(void) +{ + unsigned int id = 0; + struct systimer *const mtk_systimer = (void *)SYSTIMER_BASE; + + for (id = 0; id < SYSTIMER_CNT; id++) { + write32(&mtk_systimer->cnttval[id].con, SYST_CON_EN); + write32(&mtk_systimer->cnttval[id].con, SYST_CON_IRQ_CLR | SYST_CON_EN); + write32(&mtk_systimer->cnttval[id].con, 0); + } + + setbits32(&mtk_systimer->cntcr, REV_CLR | REV_EN); +} + +void timer_prepare(void) +{ + clrbits32((void *) SYSTIMER_BASE, COMP_FEATURE_MASK); + setbits32((void *) SYSTIMER_BASE, COMP_20_MASK); + + clear_systimer(); +}