Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25592
Change subject: nb/intel/i945: Enable and allocate 8M for TSEG ......................................................................
nb/intel/i945: Enable and allocate 8M for TSEG
TSEG can be used as a stage cache and SMM can be relocated here.
Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/i945/early_init.c 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/25592/1
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index bf486a0..7de2c73 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -192,6 +192,11 @@ gfxsize = 2; pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4));
+ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + reg8 &= ~0x7; + reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */ + pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8); + /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);