Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927
-gerrit
commit 3d0607f5130179763f867c2fdd28db42e88674f4 Author: Paul Menzel paulepanter@users.sourceforge.net Date: Tue Jun 3 22:05:33 2014 +0200
[NOTFORMERGE] mainboard/lenovo/x60/i915.c: Increase end from 800 to 1600
PGETBL_CTL differs between VBIOS (-) and native graphics init (+).
- PGETBL_CTL: 0x3ffc0001 + PGETBL_CTL: 0x3f800001
Also print what is written to PGETBL_CTL.
Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel paulepanter@users.sourceforge.net --- src/mainboard/lenovo/x60/i915.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index b41a0ba..8b5f1d9 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -136,18 +136,23 @@ int gtt_setup(unsigned int mmiobase) unsigned long PGETBL_save;
PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); PGETBL_save |= PGETBL_ENABLED; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save);
PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); PGETBL_save |= 2; /* set GTT to 256kb */ + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save);
write32(mmiobase + GFX_FLSH_CNTL, 0);
write32(mmiobase + PGETBL_CTL, PGETBL_save);
/* verify */ - if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { - printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); + PGETBL_save = read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED; + if (PGETBL_save) { + printk(BIOS_DEBUG, "gtt_setup is enabled: GTT PGETLB_CTL register: 0x%lx\n", PGETBL_save); } else { printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); return 1; @@ -351,7 +356,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, return 0; }
- setgtt(0, 800 , physbase, 4096); + setgtt(0, 1600 , physbase, 4096);
temp = READ32(PGETLB_CTL); printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp);