[coreboot-gerrit] Change in coreboot[master]: soc/amd/common: Allow the SPI base to be set for psp_verstage

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43307 )

Change subject: soc/amd/common: Allow the SPI base to be set for psp_verstage
......................................................................

soc/amd/common: Allow the SPI base to be set for psp_verstage

The PSP maps the devices into it's memory in a different fashion, so
we need to be able to use a value other than the standard x86 address.

BUG=b:159811539
TEST=Build with following patch to set the SPI speed in psp_verstage.

Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b
---
M src/soc/amd/common/block/include/amdblocks/spi.h
M src/soc/amd/common/block/spi/fch_spi.c
2 files changed, 15 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/43307/1

diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h
index d226e0c..02d2073 100644
--- a/src/soc/amd/common/block/include/amdblocks/spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/spi.h
@@ -93,5 +93,6 @@
  * settings from mainboard devicetree to configure speed and read mode.
  */
 void fch_spi_config_modes(void);
+void spi_set_base(void *base);

#endif /* __AMDBLOCKS_SPI_H__ */
diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c
index bf64c3f..04ed634 100644
--- a/src/soc/amd/common/block/spi/fch_spi.c
+++ b/src/soc/amd/common/block/spi/fch_spi.c
@@ -8,19 +8,28 @@
 #include <soc/iomap.h>
 #include <stdint.h>

+static uintptr_t spi_base;
+
+void spi_set_base(void *base)
+{
+	spi_base = (uintptr_t)base;
+}
+
 static uintptr_t fch_spi_base(void)
 {
-	uintptr_t base;
+	if (spi_base)
+		return spi_base;

-	base = lpc_get_spibase();
+	spi_base = lpc_get_spibase();

-	if (base)
-		return base;
+	if (spi_base)
+		return spi_base;

lpc_set_spibase(SPI_BASE_ADDRESS);
    lpc_enable_spi_rom(SPI_ROM_ENABLE);

-	return SPI_BASE_ADDRESS;
+	spi_base = SPI_BASE_ADDRESS;
+	return spi_base;
 }

static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm)