Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32457
Change subject: mb/google/sarien: Add psys_pmax setting to 136W ......................................................................
mb/google/sarien: Add psys_pmax setting to 136W
This patch adds the setting of psys_pmax to 136W. According to the design, Rpsys is 11.8Kohm. Here is the equation to come out the Psys_pmax value: Psys_pmax * 1.493uA/W * 11.8Kohm = 1.2V (full scale). Hence, Psys_pmax is 136W.
BUG=b:124792558 BRANCH=None TEST=emerge-sarien coreboot chromeos-bootimage & Ensure the value is passed to FSP by enabling FSP log & Boot into the OS
Change-Id: Id3f6be5f0c2346a7763195a992c0ae45faede056 Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/32457/1
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 27c0913..b086b9f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -43,6 +43,7 @@ register "SlowSlewRateForFivr" = "2" register "tdp_pl1_override" = "15" register "tdp_pl2_override" = "51" + register "psys_pmax" = "136" register "Device4Enable" = "1" # Enable eDP device register "DdiPortEdp" = "1"