[coreboot-gerrit] Change in coreboot[master]: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config.

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Kevin Chang, Kane Chen.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 )

Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config.
......................................................................

Patch Set 11: Code-Review+1

(3 comments)

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/62919/comment/cc92ada6_0c01f58b 
PS11, Line 300: static unsigned int get_aspm_control(enum ASPM_control ctl)
nit: can you add a comment similar to the one above get_l1_substate_control()
suggestion:
```
/*
 * Chip config parameter pcie_rp_aspm uses (UPD value + 1) because
 * a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure
 * that the mainboard setting does not disable ASPM incorrectly, chip 
 * config parameter values are offset by 1 with 0 meaning use FSP UPD default.
 * get_aspm_control() ensures that the right UPD value is set in fsp_params.
 * 0: Use FSP UPD default
 * 1: Disable ASPM
 * 2: L0s only
 * 3: L1 only
 * 4: L0s and L1
 * 5: Auto configuration
 */
```

File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:

https://review.coreboot.org/c/coreboot/+/62919/comment/7559894e_b834ade9 
PS11, Line 63: ntrol PcieRpL1Substates;
             : 	
`/* PCIe RP ASPM */`

https://review.coreboot.org/c/coreboot/+/62919/comment/cc424a04_679229f2 
PS11, Line 65: PcieRpAspm
nit:
`pcie_rp_aspm`