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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59929
to look at the new patch set (#2).
Change subject: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume ......................................................................
soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume
According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware...
For ACPI/legacy systems, when transitioning from the legacy to the G0 working state this register is cleared by platform firmware prior to setting the SCI_EN bit (and thus passing control to OSPM). For ACPI only platforms (where SCI_EN is always set), when transitioning from either the mechanical off (G3) or soft-off state to the G0 working state this register is cleared prior to entering the G0 working state.
This means we don't want to clear the PM1 register on resume. By clearing it the linux kernel can't correctly increment the wake count when the power button is pressed. The AMD platforms implement the _SWS ACPI methods, but the linux kernel doesn't actually use these methods.
BUG=b:172021431 TEST=suspend zork and push power button and verify power button wake_count increments. Verified other wake sources still work.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 --- M src/soc/amd/cezanne/fch.c M src/soc/amd/common/block/cpu/smm/finalize.c M src/soc/amd/picasso/fch.c M src/soc/amd/stoneyridge/romstage.c 4 files changed, 2 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/59929/2