[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Configure FSP UPDs for minimum assertion widths

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Nick Vaccaro, Sridhar Siricilla, Meera Ravindranath, Patrick Rudolph, Karthik Ramasubramanian.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51846 )

Change subject: soc/intel/alderlake: Configure FSP UPDs for minimum assertion widths
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Patch Set 2:

(1 comment)

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/51846/comment/98476fe8_8eacc478 
PS2, Line 316: 	/*
             : 	 * SLP_S3 Minimum Assertion Width Policy
             : 	 *  1 = 60us
             : 	 *  2 = 1ms
             : 	 *  3 = 50ms (default)
             : 	 *  4 = 2s
             : 	 */
             : 	uint8_t PchPmSlpS3MinAssert;
             : 
             : 	/*
             : 	 * SLP_S4 Minimum Assertion Width Policy
             : 	 *  1 = 1s (default)
             : 	 *  2 = 2s
             : 	 *  3 = 3s
             : 	 *  4 = 4s
             : 	 */
             : 	uint8_t PchPmSlpS4MinAssert;
             : 
             : 	/*
             : 	 * SLP_SUS Minimum Assertion Width Policy
             : 	 *  1 = 0ms
             : 	 *  2 = 500ms
             : 	 *  3 = 1s
             : 	 *  4 = 4s (default)
             : 	 */
             : 	uint8_t PchPmSlpSusMinAssert;
             : 
             : 	/*
             : 	 * SLP_A Minimum Assertion Width Policy
             : 	 *  1 = 0ms
             : 	 *  2 = 4s
             : 	 *  3 = 98ms
             : 	 *  4 = 2s (default)
             : 	 */
             : 	uint8_t PchPmSlpAMinAssert;
             : 
             : 	/*
             : 	 * PCH PM Reset Power Cycle Duration
             : 	 *  0 = 4s (default)
             : 	 *  1 = 1s
             : 	 *  2 = 2s
             : 	 *  3 = 3s
             : 	 *  4 = 4s
             : 	 *
             : 	 * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
             : 	 * stretch duration programmed in the following registers:
             : 	 *  - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
             : 	 *  - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
             : 	 *  - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
             : 	 *  - PM_CFG.SLP_LAN_MIN_ASST_WDTH
             : 	 */
             : 	uint8_t PchPmPwrCycDur;
suggestion: Could we define these all as enums defined in terms of some base unit, like microseconds? example for Slp_S3#:

```
enum {
        SlpS3_MinAssert_60us = 60,
        SlpS3_MinAssert_1ms = 1 * USECS_PER_MSEC,
        SlpS3_MinAssert_50ms = 50 * USECS_PER_MSEC,
        SlpS3_MinAssert_2s = 2 * MSECS_PER_USEC * MSECS_PER_SEC
} PchPmSlpS3MinAssert;
```

Then if the field is 0 (because it's not used in the devicetree), you set the default in fsp_params.c, e.g.:

```
if (!config->PchPmSlpS3MinAssert)
        config->PchPmSlpS3MinAssert = SlpS3_MinAssert_50ms; /* Default */
```