Attention is currently required from: Felix Singer, Michał Kopeć, Angel Pons.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 )
Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ......................................................................
Patch Set 16:
(4 comments)
Patchset:
PS16: a
File src/mainboard/clevo/tgl-u/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/62498/comment/d444c89e_8ce69e5a PS3, Line 6: GPD9 GPD3? GPD9 is SLP_WLAN#
File src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c:
https://review.coreboot.org/c/coreboot/+/62498/comment/9ec5a169_2eccf51b PS6, Line 129: //PAD_CFG_TERM_GPO(GPP_U4, 1, NONE, DEEP), /* DGPU_RST#_PCH */ : //PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, DEEP), /* DGPU_PWR_EN */ :
We thought some options were added to FSP so that it leaves GPIOs alone. […]
There is a option with three possible degrees of "leaving gpios alone". TGL currently only sets the first one.
``` Help "Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings before moved to FSP. Available configurations 0: Disable;1: Level 1 - skips GpioSetNativePadByFunction;Level 2 - skips GpioSetNativePadByFunction and GpioSetPadMode" ```
``` src/soc/intel/tigerlake/romstage/fsp_params.c: m_cfg->GpioOverride = 0x1; ```
File src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62498/comment/7eeed456_b93acbe6 PS16, Line 13: params->CpuPcieRpLtrEnable[0] = 1; : params->CpuPcieRpSlotImplemented[0] = 1;
No devicetree settings for these?
not yet, unfortunately; there is a change from me for that somewhere