[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support

[Paul Menzel (Code Review)]

Attention is currently required from: Jian Tong, Karthik Ramasubramanian, Subrata Banik.

Paul Menzel has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/84177?usp=email )

Change subject: mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support
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Patch Set 3:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84177/comment/a4a9fb2d_af1e7ae7?usp... :
PS3, Line 9: Because of RTS5227 don't support L0s, so set to ASPM_L1.
What is the result of that? Errors in the log? Non-working device?

Then maybe:
> According to X the RTS5227 does not support L0s, so set it to ASPM_L1.

https://review.coreboot.org/c/coreboot/+/84177/comment/e42195d3_8656a9de?usp... :
PS3, Line 12: TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
How can the change be verified?