[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC

[Subrata Banik (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim.

Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email )

Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
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Patch Set 70:

(1 comment)

File src/soc/intel/pantherlake/include/soc/gpio_defs.h:

https://review.coreboot.org/c/coreboot/+/83789/comment/dab5768f_af8d4fde?usp... :
PS49, Line 260: GPP_E_OFFSET
> Subrata, I just contacted our EDS owner and was told that GPP_E0 is a no connect pin (not bonded out to the package) in PTL. In addition, he points out to reference PTL GPIO Implementation doc for details (#817954). Can you try if you can see this document?

if you are saying GPP_E0 doesn't even exist for PTL then first PIN should be `(PAD_CFG_DW0_xxgpp_e_1)` and start offset should be 0x9b0