Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42440 )
Change subject: soc/intel/cannonlake: Add PchPmPwrCycDur to chip options ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42440/4/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/42440/4/src/soc/intel/cannonlake/ch... PS4, Line 316: * 1 = 1s
maybe add a note that 0 = FSP will program the default 0 ?
Done
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/ch... PS3, Line 321: uint8_t PchPmPwrCycDur;
@Furquan, your comments are correct.
Done