[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/block/lpc: Add lpc_initialize_spi_bar()

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41247 )

Change subject: soc/amd/common/block/lpc: Add lpc_initialize_spi_bar()
......................................................................

soc/amd/common/block/lpc: Add lpc_initialize_spi_bar()

This change adds helper function lpc_initialize_spi_bar() which sets
MMIO base for SPI controller and ROM enable bits. This is equivalent
to renaming of lpc_set_spibase() to
lpc_initialize_spi_bar(). Additionally, lpc_set_spibase() is updated
to just set the MMIO base for SPI controller. This split is done to
allow setting of MMIO base independent of ROM enable bits. On
platforms like Picasso, eSPI base is determined by the same register
and hence eSPI can set the BAR without having to touch the enable
bits.

Signed-off-by: Furquan Shaikh 
Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be
---
M src/soc/amd/common/block/include/amdblocks/lpc.h
M src/soc/amd/common/block/lpc/lpc_util.c
M src/soc/amd/picasso/southbridge.c
M src/soc/amd/stoneyridge/southbridge.c
4 files changed, 36 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/41247/1

diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index d7a455a..c915f30 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -179,6 +179,19 @@
 int lpc_set_wideio_range(uint16_t start, uint16_t size);

uintptr_t lpc_get_spibase(void);
-void lpc_set_spibase(uint32_t base, uint32_t enable);
+
+/*
+ * Sets MMIO base address for SPI controller and eSPI controller (if supported by platform).
+ *
+ * eSPI base = SPI base + 0x10000
+ */
+void lpc_set_spibase(uint32_t base);
+
+/*
+ * Initializes SPI base addres register which includes the following two components:
+ * base = MMIO base for SPI controller and eSPI controller (if supported by platform).
+ * enable = ROM enable (SPI_ROM_ENABLE, SPI_ROM_ALT_ENABLE)
+ */
+void lpc_initialize_spi_bar(uint32_t base, uint32_t enable);

#endif /* __AMDBLOCKS_LPC_H__ */
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 97ef17c..cc9ed48 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -322,19 +322,35 @@
    return (uintptr_t)base;
 }

-void lpc_set_spibase(u32 base, u32 enable)
+void lpc_set_spibase(uint32_t base)
 {
-	u32 reg32;
+	uint32_t reg32;
+
+	reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);
+
+	reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */
+	reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);
+
+	pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32);
+}
+
+static void lpc_set_rom_enable(uint32_t enable)
+{
+	uint32_t reg32;

/* only two types of CS# enables are allowed */
    enable &= SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE;

reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);

-	reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */
    reg32 &= ~(SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE);
    reg32 |= enable;
-	reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);

pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32);
 }
+
+void lpc_initialize_spi_bar(uint32_t base, uint32_t enable)
+{
+	lpc_set_spibase(base);
+	lpc_set_rom_enable(enable);
+}
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 73ab03b..6d6a00d 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -207,7 +207,7 @@
    if (base)
    	return base;

-	lpc_set_spibase(SPI_BASE_ADDRESS, SPI_ROM_ENABLE);
+	lpc_initialize_spi_bar(SPI_BASE_ADDRESS, SPI_ROM_ENABLE);
    return SPI_BASE_ADDRESS;
 }

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index ccdedf4..acaeddb 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -265,7 +265,7 @@
    if (base)
    	return base;

-	lpc_set_spibase(SPI_BASE_ADDRESS, SPI_ROM_ENABLE);
+	lpc_initialize_spi_bar(SPI_BASE_ADDRESS, SPI_ROM_ENABLE);
    return SPI_BASE_ADDRESS;
 }