Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46994 )
Change subject: nb/intel/haswell: Drop incorrect MMIO_PAVP_MSG write ......................................................................
nb/intel/haswell: Drop incorrect MMIO_PAVP_MSG write
This write was copied from Sandy Bridge. Neither Haswell reference code nor Broadwell perform this write. Therefore, it seems safe to remove it.
Change-Id: I8869ff3e66362d9910235c554c3a07e91f479a82 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46994 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/northbridge.c 1 file changed, 0 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index c59dce7..130c0ff 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -547,9 +547,6 @@ /* Configure turbo power limits 1ms after reset complete bit. */ mdelay(1); set_power_limits(28); - - /* Set here before graphics PM init. */ - MCHBAR32(MMIO_PAVP_MSG) = 0x00100001; }
static struct device_operations mc_ops = {