Francis Rowe (info@gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927
-gerrit
commit a19fc9d1779b80e9fd4e244c1f37baecb0e0d9a3 Author: Paul Menzel paulepanter@users.sourceforge.net Date: Thu Jun 5 22:45:35 2014 +0200
intel/i945/gma: Place GTT below top of memory
Since commit 17fec8a0 [1]
drm/i915: Use Graphics Base of Stolen Memory on all gen3+
present in the Linux kernel since version 3.12, 3D does not work anymore [2].
Comparing the graphics registers, in this case that means output of `intel_reg_dumper`, the vendor Video BIOS is setting the register PGTBL_CTL/PGETBL_CTL, only documented in the i965 datasheet [3], to `0x3ffc0001` on a system with 1 GB of RAM, while native graphics init sets it to `0x3f800001`.
Currently native graphis init sets the GTT right above the base address of stolen memory. The Video BIOS sets it below the top of memory. The Linux Intel driver expects it to be below top of memory, so do it this way, by setting the address to TOM minus the size of the GTT, which is hardcoded to 256 KiB.
As `PGETBL_CTL` is zero by default, reading its value in the beginning is not necessary and is only confusing. Make it clear that the code calculates the value.
There is still an error PTE error reported during boot, but 3D works with Linux 3.12+ and no user visible problems are shown.
[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=1... [2] https://bugs.freedesktop.org/show_bug.cgi?id=79038 [3] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_1... Intel ® 965 Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller Programmer’s Reference Manual Volume 1: Graphics Core Revision 1.0a
Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel paulepanter@users.sourceforge.net Signed-off-by: Francis Rowe info@gluglug.org.uk --- src/northbridge/intel/i945/gma.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 140aaa7..e922013 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -52,11 +52,19 @@ static int gtt_setup(unsigned int mmiobase) { unsigned long PGETBL_save; - - PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; + unsigned long tom; // top of memory + + /* + * The Video BIOS places the GTT right below top of memory. + * + * It is not documented in the Intel 945 datasheet, but the Intel + * developers said that it is normally placed there. + * + * TODO: Add option to make the GTT size runtime configurable + */ + tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24; + PGETBL_save = tom - 256 * KiB; PGETBL_save |= PGETBL_ENABLED; - - PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; PGETBL_save |= 2; /* set GTT to 256kb */
write32(mmiobase + GFX_FLSH_CNTL, 0); @@ -416,7 +424,7 @@ static void gma_func0_init(struct device *dev) );
int err; - err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, + err = intel_gma_init(conf, pci_read_config32(dev, BSM) & ~0xf, iobase, mmiobase, graphics_base); if (err == 0) gfx_set_init_done(1);