Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58197 )
Change subject: Update Cezanne FSP-M UPD definition ......................................................................
Update Cezanne FSP-M UPD definition
Update UPD to include option for FSP to de-assert PCIe reset GPIOs. This is already off by default with a newer FSP (unused UPD space is all 0s). This update bumps PcdImageRevisionBuildNumber to 2
BUG=b:199780346 TEST=Verify toggling this value is reflected in FSP
Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a Signed-off-by: Matt Papageorge matthewpapa07@gmail.com --- M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/58197/1
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 7cb788e..f21ca42 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -26,7 +26,8 @@ /** Offset 0x0078**/ uint32_t serial_port_refclk; /** Offset 0x007C**/ uint32_t serial_reserved; /** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52]; - /** Offset 0x0358**/ uint8_t pcie_reserved[52]; + /** Offset 0x0358**/ uint8_t fsp_owns_pcie_resets; + /** Offset 0x0359**/ uint8_t pcie_reserved[51]; /** Offset 0x038C**/ uint32_t ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT]; /** Offset 0x03A0**/ uint8_t ddi_reserved[6]; /** Offset 0x03A6**/ uint8_t ccx_down_core_mode;