Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Christian Walter, Jes Klinke, Julius Werner, Patrick Rudolph, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43741
to look at the new patch set (#7).
Change subject: Enable long cr50 ready pulses for Tigerlake systems ......................................................................
Enable long cr50 ready pulses for Tigerlake systems
New Kconfig setting TPM_BOARD_CFG controls new code in verstage, which will program the given value into a register, provided that Cr50 firmware is new enough to support the register.
Knowledge of whether the register was set or not is propagated through CAR and CBMEM to the point in early ramstage where parameters are passed to FSP. For Volteer (and future Tigerlake boards) we enable mode S0i3.4 only if we know that the Cr50 is generating 100us interrupt pulses.
Signed-off-by: Jes Bodi Klinke jbk@chromium.org Change-Id: If83188fd09fe69c2cda4ce1a8bf5b2efe1ca86da Bug: b:154333137 --- M src/arch/x86/car.ld M src/commonlib/include/commonlib/cbmem_id.h M src/drivers/spi/tpm/tpm.c M src/drivers/spi/tpm/tpm.h M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/security/tpm/tss/vendor/cr50/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 10 files changed, 179 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/43741/7