Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11040
-gerrit
commit c37c82989ebd398a8c974b0fde2bb9fd54a17c6a Author: Yen Lin yelin@nvidia.com Date: Thu May 7 12:28:43 2015 -0700
t210: Enable WRAP to INCR burst type conversion in MSELECT
Enable WRAP to INCR burst type conversion in MSELECT. MSELECT CONFIG register can only be accessed by CPU. So do it in ramstage when CPU is started.
BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel
Change-Id: Iee05531c45e566f47af24870be6068247c2d9a00 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 21d9e4d3a8827f7bba57c03ca36b702aaba1ce20 Original-Change-Id: I6a241455b28f24b8756ad09bf7605a2e7e52af57 Original-Signed-off-by: Yen Lin yelin@nvidia.com Original-Reviewed-on: https://chromium-review.googlesource.com/282418 Original-Reviewed-by: Tom Warren twarren@nvidia.com Original-Reviewed-by: Furquan Shaikh furquan@chromium.org --- src/soc/nvidia/tegra210/include/soc/addressmap.h | 1 + src/soc/nvidia/tegra210/ramstage.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+)
diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h index 66888c6..c3af00c 100644 --- a/src/soc/nvidia/tegra210/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h @@ -35,6 +35,7 @@ enum { TEGRA_ARM_PERIPHBASE = 0x50040000, TEGRA_GICD_BASE = 0x50041000, TEGRA_GICC_BASE = 0x50042000, + TEGRA_MSELECT_CONFIG = 0x50060000, TEGRA_ARM_DISPLAYA = 0x54200000, TEGRA_ARM_DISPLAYB = 0x54240000, TEGRA_DSIA_BASE = 0x54300000, diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 7838c69..f37c817 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -31,8 +31,30 @@ void arm64_arch_timer_init(void) set_cntfrq(freq); }
+static void mselect_enable_wrap(void) +{ + uint32_t reg; + +#define ERR_RESP_EN_SLAVE1 (0x1 << 24) +#define ERR_RESP_EN_SLAVE2 (0x1 << 25) +#define WRAP_TO_INCR_SLAVE0 (0x1 << 27) +#define WRAP_TO_INCR_SLAVE1 (0x1 << 28) +#define WRAP_TO_INCR_SLAVE2 (0x1 << 29) + + reg = read32((void *)TEGRA_MSELECT_CONFIG); + /* Disable error mechanism */ + reg &= ~(ERR_RESP_EN_SLAVE1 | ERR_RESP_EN_SLAVE2); + /* Enable WRAP type conversion */ + reg |= (WRAP_TO_INCR_SLAVE0 | WRAP_TO_INCR_SLAVE1 | + WRAP_TO_INCR_SLAVE2); + write32((void *)TEGRA_MSELECT_CONFIG, reg); +} + void arm64_soc_init(void) { + /* Enable WRAP to INCR burst type conversion in MSELECT */ + mselect_enable_wrap(); + trustzone_region_init();
tegra210_mmu_init();