[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/mtl: Fill in SPD data on both channels of DDR5 memory

[Michał Kopeć (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Kapil Porwal, Tarun, Tim Crawford.

Michał Kopeć has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/82733?usp=email )

Change subject: soc/intel/mtl: Fill in SPD data on both channels of DDR5 memory
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Patch Set 1: Code-Review+1