HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16623
-gerrit
commit 3ba6500c33d64a9bcce2d35411bdfc6bdcfa960f Author: Elyes HAOUAS ehaouas@noos.fr Date: Sat Sep 17 09:42:40 2016 +0200
src/northbridge: Add space around operators
Change-Id: I87f8978b8ec6ddc11dd66a77cbb630e057f9831b Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/northbridge/amd/agesa/family10/amdfam10.h | 4 +- src/northbridge/amd/agesa/family10/northbridge.c | 20 +- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 10 +- src/northbridge/amd/agesa/family12/northbridge.c | 4 +- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 14 +- src/northbridge/amd/agesa/family15/northbridge.c | 20 +- src/northbridge/amd/agesa/family15rl/northbridge.c | 20 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 20 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 20 +- src/northbridge/amd/agesa/oem_s3.c | 2 +- src/northbridge/amd/amdfam10/acpi.c | 22 +-- src/northbridge/amd/amdfam10/amdfam10.h | 4 +- src/northbridge/amd/amdfam10/debug.c | 8 +- src/northbridge/amd/amdfam10/early_ht.c | 2 +- src/northbridge/amd/amdfam10/get_pci1234.c | 8 +- src/northbridge/amd/amdfam10/ht_config.c | 20 +- src/northbridge/amd/amdfam10/northbridge.c | 10 +- src/northbridge/amd/amdfam10/raminit.h | 2 +- src/northbridge/amd/amdfam10/raminit_amdmct.c | 2 +- .../amd/amdfam10/raminit_sysinfo_in_ram.c | 4 +- src/northbridge/amd/amdht/AsPsNb.c | 8 +- src/northbridge/amd/amdht/h3finit.c | 2 +- src/northbridge/amd/amdht/h3ncmn.c | 46 ++--- src/northbridge/amd/amdk8/acpi.c | 24 +-- src/northbridge/amd/amdk8/coherent_ht.c | 70 +++---- src/northbridge/amd/amdk8/debug.c | 6 +- src/northbridge/amd/amdk8/early_ht.c | 2 +- src/northbridge/amd/amdk8/f.h | 4 +- src/northbridge/amd/amdk8/get_sblk_pci1234.c | 10 +- src/northbridge/amd/amdk8/incoherent_ht.c | 58 +++--- src/northbridge/amd/amdk8/northbridge.c | 12 +- src/northbridge/amd/amdk8/raminit.c | 22 +-- src/northbridge/amd/amdk8/raminit_f.c | 52 ++--- src/northbridge/amd/amdk8/raminit_f_dqs.c | 72 +++---- src/northbridge/amd/amdmct/mct/mct.h | 196 +++++++++--------- src/northbridge/amd/amdmct/mct/mct_d.c | 78 ++++---- src/northbridge/amd/amdmct/mct/mct_d.h | 220 ++++++++++----------- src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 6 +- src/northbridge/amd/amdmct/mct/mctchi_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 24 +-- src/northbridge/amd/amdmct/mct/mctecc_d.c | 4 +- src/northbridge/amd/amdmct/mct/mctgr.c | 4 +- src/northbridge/amd/amdmct/mct/mctmtr_d.c | 24 +-- src/northbridge/amd/amdmct/mct/mctndi_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctpro_d.c | 12 +- src/northbridge/amd/amdmct/mct/mctsrc.c | 40 ++-- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct/mctsrc2p.c | 6 +- src/northbridge/amd/amdmct/mct/mcttmrl.c | 10 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 88 ++++----- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 220 ++++++++++----------- src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 6 +- src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c | 4 +- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 24 +-- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 4 +- src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c | 24 +-- src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 4 +- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 6 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 38 ++-- src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | 6 +- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 10 +- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 10 +- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 72 +++---- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 110 +++++------ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 4 +- src/northbridge/amd/cimx/rd890/late.c | 2 +- src/northbridge/amd/gx2/northbridgeinit.c | 88 ++++----- src/northbridge/amd/gx2/raminit.c | 6 +- src/northbridge/amd/lx/northbridge.c | 2 +- src/northbridge/amd/lx/raminit.c | 14 +- src/northbridge/amd/pi/00630F01/northbridge.c | 20 +- src/northbridge/amd/pi/00660F01/northbridge.c | 12 +- src/northbridge/amd/pi/00730F01/northbridge.c | 20 +- src/northbridge/intel/e7501/debug.c | 4 +- src/northbridge/intel/e7505/debug.c | 4 +- src/northbridge/intel/e7505/raminit.c | 4 +- .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 2 +- src/northbridge/intel/fsp_rangeley/northbridge.c | 4 +- src/northbridge/intel/fsp_rangeley/udelay.c | 2 +- src/northbridge/intel/fsp_sandybridge/acpi.c | 2 +- .../intel/fsp_sandybridge/acpi/hostbridge.asl | 2 +- src/northbridge/intel/fsp_sandybridge/chip.h | 2 +- .../intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 2 +- src/northbridge/intel/fsp_sandybridge/gma.c | 4 +- .../intel/fsp_sandybridge/northbridge.c | 4 +- src/northbridge/intel/fsp_sandybridge/udelay.c | 2 +- src/northbridge/intel/gm45/northbridge.c | 14 +- src/northbridge/intel/haswell/acpi.c | 2 +- src/northbridge/intel/haswell/acpi/hostbridge.asl | 2 +- src/northbridge/intel/haswell/chip.h | 2 +- src/northbridge/intel/haswell/gma.c | 4 +- src/northbridge/intel/i3100/pciexp_porta.c | 2 +- src/northbridge/intel/i3100/pciexp_porta_ep80579.c | 2 +- src/northbridge/intel/i3100/raminit.c | 90 ++++----- src/northbridge/intel/i3100/raminit_ep80579.c | 2 +- src/northbridge/intel/i440bx/raminit.c | 2 +- src/northbridge/intel/i5000/raminit.h | 10 +- src/northbridge/intel/i82830/smihandler.c | 16 +- src/northbridge/intel/i945/acpi.c | 2 +- src/northbridge/intel/i945/debug.c | 2 +- src/northbridge/intel/i945/early_init.c | 2 +- src/northbridge/intel/i945/gma.c | 4 +- src/northbridge/intel/i945/northbridge.c | 6 +- src/northbridge/intel/i945/raminit.c | 74 +++---- src/northbridge/intel/i945/rcven.c | 2 +- src/northbridge/intel/nehalem/acpi/hostbridge.asl | 2 +- src/northbridge/intel/nehalem/chip.h | 2 +- src/northbridge/intel/nehalem/gma.c | 2 +- src/northbridge/intel/pineview/northbridge.c | 4 +- src/northbridge/intel/sandybridge/acpi.c | 2 +- .../intel/sandybridge/acpi/hostbridge.asl | 2 +- src/northbridge/intel/sandybridge/chip.h | 2 +- src/northbridge/intel/sandybridge/gma.c | 6 +- src/northbridge/intel/sandybridge/northbridge.c | 10 +- src/northbridge/intel/sandybridge/udelay.c | 2 +- src/northbridge/intel/x4x/northbridge.c | 8 +- src/northbridge/intel/x4x/raminit_ddr2.c | 2 +- src/northbridge/via/cn700/raminit.c | 8 +- src/northbridge/via/cn700/vga.c | 22 +-- src/northbridge/via/cx700/agp.c | 2 +- src/northbridge/via/cx700/early_smbus.c | 2 +- src/northbridge/via/cx700/lpc.c | 2 +- src/northbridge/via/cx700/raminit.c | 8 +- src/northbridge/via/cx700/vga.c | 10 +- src/northbridge/via/vx800/dev_init.c | 144 +++++++------- src/northbridge/via/vx800/dram_init.h | 2 +- src/northbridge/via/vx800/drdy_bl.c | 32 +-- src/northbridge/via/vx800/freq_setting.c | 14 +- src/northbridge/via/vx800/lpc.c | 7 +- src/northbridge/via/vx800/uma_ram_setting.c | 8 +- src/northbridge/via/vx800/vga.c | 18 +- 133 files changed, 1316 insertions(+), 1317 deletions(-)
diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h index b1dab41..27f78a3 100644 --- a/src/northbridge/amd/agesa/family10/amdfam10.h +++ b/src/northbridge/amd/agesa/family10/amdfam10.h @@ -87,8 +87,8 @@ #endif
#ifdef __PRE_RAM__ -#if NODE_NUMS==64 - #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#if NODE_NUMS == 64 + #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 53ddc0e..0d495b7 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -100,7 +100,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) { u32 index;
- for (index=0; index<256; index++) { + for (index = 0; index < 256; index++) { if ((sysconf.conf_io_addrx[index+4] == 0)) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); @@ -116,7 +116,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) { u32 index;
- for (index=0; index<64; index++) { + for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); @@ -167,7 +167,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
/* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? @@ -182,7 +182,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -193,10 +193,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
/* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -609,7 +609,7 @@ static void amdfam10_domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -685,7 +685,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -877,7 +877,7 @@ static void sysconf_init(device_t dev) // first node
unsigned ht_c_index;
- for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { sysconf.ht_c_conf_bus[ht_c_index] = 0; }
@@ -1027,7 +1027,7 @@ static void cpu_bus_scan(device_t dev) devn = CONFIG_CDB+i; pbus = dev_mc->bus; #if CONFIG_CBB && (NODE_NUMS > 32) - if (i>=32) { + if (i >= 32) { busn--; devn-=32; pbus = pci_domain->link_list->next); diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 7afa39d..129ec60 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -54,12 +54,12 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
/* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i=0; i<nodes; i++){ + for (i = 0; i < nodes; i++){ dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); } @@ -73,7 +73,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, device_t dev;
/* io range allocation */ - for (i=0; i<nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); @@ -87,7 +87,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) #if 0 u32 index;
- for (index=0; index<256; index++) { + for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); @@ -103,7 +103,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) #if 0 u32 index;
- for (index=0; index<64; index++) { + for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 1526972..12bb055 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -41,7 +41,7 @@ static device_t __f0_dev[FX_DEVS]; static device_t __f1_dev[FX_DEVS]; static device_t __f2_dev[FX_DEVS]; static device_t __f4_dev[FX_DEVS]; -static unsigned fx_devs=0; +static unsigned fx_devs = 0;
static device_t get_node_pci(u32 nodeid, u32 fn) { @@ -485,7 +485,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index 6db2b95..1953612 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -54,12 +54,12 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
/* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i=0; i<nodes; i++){ + for (i = 0; i < nodes; i++){ dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); } @@ -73,7 +73,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, device_t dev;
/* io range allocation */ - for (i=0; i<nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); @@ -87,7 +87,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) #if 0 u32 index;
- for (index=0; index<256; index++) { + for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); @@ -103,7 +103,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) #if 0 u32 index;
- for (index=0; index<64; index++) { + for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); @@ -158,7 +158,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi ********************************************************************/ u32 map_oprom_vendev(u32 vendev) { - u32 new_vendev=vendev; + u32 new_vendev = vendev;
switch(vendev) { case 0x10029809: @@ -168,7 +168,7 @@ u32 map_oprom_vendev(u32 vendev) case 0x10029805: case 0x10029804: case 0x10029803: - new_vendev=0x10029802; + new_vendev = 0x10029802; break; }
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 0c14bdd..ae6dad12 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -80,7 +80,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 @@ -94,7 +94,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -104,10 +104,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -138,7 +138,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); }
static u32 f1_read_config32(unsigned reg) @@ -636,7 +636,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -703,7 +703,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -1062,7 +1062,7 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
for (j = 0; j <= siblings; j++ ) { @@ -1087,14 +1087,14 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } #if CONFIG_CPU_AMD_SOCKET_G34 u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0); #else u32 apic_id = (i * core_max) + j + lapicid_start; #endif - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index d1560b7..37ad1a5 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -80,7 +80,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 @@ -94,7 +94,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -104,10 +104,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -138,7 +138,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); }
static u32 f1_read_config32(unsigned reg) @@ -630,7 +630,7 @@ static void domain_read_resources(struct device *dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -697,7 +697,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -1050,7 +1050,7 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
for (j = 0; j <= siblings; j++ ) { @@ -1077,10 +1077,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7b57cc3..af63619 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -79,7 +79,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 @@ -93,7 +93,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -103,10 +103,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -137,7 +137,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); }
static u32 f1_read_config32(unsigned reg) @@ -629,7 +629,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -696,7 +696,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -1049,7 +1049,7 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
for (j = 0; j <= siblings; j++ ) { @@ -1076,10 +1076,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 28302ef..ce0a94c 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -79,7 +79,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 @@ -93,7 +93,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -103,10 +103,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -137,7 +137,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); }
static u32 f1_read_config32(unsigned reg) @@ -644,7 +644,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -711,7 +711,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -1066,7 +1066,7 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
for (j = 0; j <= siblings; j++ ) { @@ -1093,10 +1093,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index 4f2788e..fcf8ada 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -23,7 +23,7 @@ #include <AGESA.h>
typedef enum { - S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeNonVolatile = 0, ///< NonVolatile Data Type S3DataTypeMTRR ///< MTRR storage } S3_DATA_TYPE;
diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 51da7d6..ba1007d 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -96,7 +96,7 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res) */ if ((basek+sizek)<1024) return;
- if (basek<1024) { + if (basek < 1024) { sizek -= 1024 - basek; basek = 1024; } @@ -158,9 +158,9 @@ static unsigned long acpi_fill_slit(unsigned long current) *p = (u8) nodes; p += 8;
- for (i=0;i<nodes;i++) { - for (j=0;j<nodes; j++) { - if (i==j) + for (i = 0; i < nodes; i++) { + for (j = 0; j < nodes; j++) { + if (i == j) p[i*nodes+j] = 10; else p[i*nodes+j] = 16; @@ -221,7 +221,7 @@ void northbridge_acpi_write_vars(device_t device)
acpigen_write_name("BUSN"); acpigen_write_package(HC_NUMS); - for (i=0; i<HC_NUMS; i++) { + for (i = 0; i < HC_NUMS; i++) { acpigen_write_dword(sysconf.ht_c_conf_bus[i]); } // minus the opcode @@ -231,7 +231,7 @@ void northbridge_acpi_write_vars(device_t device)
acpigen_write_package(HC_NUMS * 4);
- for (i=0;i<(HC_NUMS*2);i++) { // FIXME: change to more chain + for (i = 0; i<(HC_NUMS*2); i++) { // FIXME: change to more chain acpigen_write_dword(sysconf.conf_mmio_addrx[i]); //base acpigen_write_dword(sysconf.conf_mmio_addr[i]); //mask } @@ -242,7 +242,7 @@ void northbridge_acpi_write_vars(device_t device)
acpigen_write_package(HC_NUMS * 2);
- for (i=0;i<HC_NUMS;i++) { // FIXME: change to more chain + for (i = 0; i < HC_NUMS; i++) { // FIXME: change to more chain acpigen_write_dword(sysconf.conf_io_addrx[i]); acpigen_write_dword(sysconf.conf_io_addr[i]); } @@ -273,10 +273,10 @@ void northbridge_acpi_write_vars(device_t device)
acpigen_write_package(HC_POSSIBLE_NUM);
- for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { acpigen_write_dword(sysconf.pci1234[i]); } - for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x00000000); } // minus the opcode @@ -286,10 +286,10 @@ void northbridge_acpi_write_vars(device_t device)
acpigen_write_package(HC_POSSIBLE_NUM);
- for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { acpigen_write_dword(sysconf.hcdn[i]); } - for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x20202020); } // minus the opcode diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 4c3aec6..6c0a635 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -967,8 +967,8 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #include "nums.h"
#ifdef __PRE_RAM__ -#if NODE_NUMS==64 - #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#if NODE_NUMS == 64 + #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index e01c44d..2525fd8 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -95,7 +95,7 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) printk(BIOS_DEBUG, "\n%04x:",i); } val = pci_read_config32(dev, i); - for (j=0;j<4;j++) { + for (j = 0; j < 4; j++) { printk(BIOS_DEBUG, " %02x", val & 0xff); val >>= 8; } @@ -121,7 +121,7 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, int j; printk(BIOS_DEBUG, "\n%02x:",i); val = pci_read_config32_index_wait(dev, index_reg, i); - for (j=0;j<4;j++) { + for (j = 0; j < 4; j++) { printk(BIOS_DEBUG, " %02x", val & 0xff); val >>= 8; } @@ -287,7 +287,7 @@ static inline void dump_io_resources(u32 port) int i; udelay(2000); printk(BIOS_DEBUG, "%04x:\n", port); - for (i=0;i<256;i++) { + for (i = 0; i < 256; i++) { u8 val; if ((i & 0x0f) == 0) { printk(BIOS_DEBUG, "%02x:", i); @@ -305,7 +305,7 @@ static inline void dump_mem(u32 start, u32 end) { u32 i; printk(BIOS_DEBUG, "dump_mem:"); - for (i=start;i<end;i++) { + for (i = start; i < end; i++) { if ((i & 0xf)==0) { printk(BIOS_DEBUG, "\n%08x:", i); } diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index a1b411f..61a11eb 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -96,7 +96,7 @@ static void enumerate_ht_chain(void) pci_devfn_t devx;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (next_unitid>=0x18) { + if (next_unitid >= 0x18) { if (!end_used) { next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c index a6f679e..11f1589 100644 --- a/src/northbridge/amd/amdfam10/get_pci1234.c +++ b/src/northbridge/amd/amdfam10/get_pci1234.c @@ -73,7 +73,7 @@ void get_pci1234(void) //2. so at the same time we need update hsdn with hcdn_reg here // printk(BIOS_DEBUG, "sysconf.ht_c_num = %02d\n", sysconf.ht_c_num);
- for (j=0;j<sysconf.ht_c_num;j++) { + for (j = 0; j < sysconf.ht_c_num; j++) { u32 dwordx; dwordx = sysconf.ht_c_conf_bus[j]; // printk(BIOS_DEBUG, "sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]); @@ -86,7 +86,7 @@ void get_pci1234(void) if ((dwordx & 1)) { // We need to find out the number of HC // for exact match - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((dwordx & 0x7fc) == (sysconf.pci1234[i] & 0x7fc)) { // same node and same linkn sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; @@ -94,7 +94,7 @@ void get_pci1234(void) } } // for 0xffc match or same node - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((dwordx & 0x7fc) == (dwordx & sysconf.pci1234[i] & 0x7fc)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; @@ -104,7 +104,7 @@ void get_pci1234(void) } }
- for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if (!(sysconf.pci1234[i] & 1)) { sysconf.pci1234[i] = 0; sysconf.hcdn[i] = 0x20202020; diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c index 9603223..01982b3 100644 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -56,7 +56,7 @@ void set_config_map_reg(struct bus *link) tempreg = ((nodeid & 0x30) << (12-4)) | ((nodeid & 0xf) << 4) | 3; tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8);
- for (i=0; i < sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); } @@ -67,7 +67,7 @@ void clear_config_map_reg(struct bus *link) u32 i; u32 ht_c_index = get_ht_c_index(link);
- for (i=0; i < sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); } @@ -86,13 +86,13 @@ static u32 get_ht_c_index_by_key(u32 key, sys_info_conf_t *sysinfo) { u32 ht_c_index = 0;
- for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == key) { return ht_c_index; } }
- for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { if (sysinfo->ht_c_conf_bus[ht_c_index] == 0) { return ht_c_index; } @@ -127,7 +127,7 @@ u32 get_io_addr_index(u32 nodeid, u32 linkn) { u32 index;
- for (index=0; index<256; index++) { + for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); @@ -142,7 +142,7 @@ u32 get_mmio_addr_index(u32 nodeid, u32 linkn) { u32 index;
- for (index=0; index<64; index++) { + for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); @@ -198,7 +198,7 @@ void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
/* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? @@ -213,7 +213,7 @@ void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -224,9 +224,9 @@ void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min,
/* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 42647b1..b5126fa 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -65,7 +65,7 @@ static device_t __f0_dev[FX_DEVS]; device_t __f1_dev[FX_DEVS]; static device_t __f2_dev[FX_DEVS]; static device_t __f4_dev[FX_DEVS]; -static unsigned fx_devs=0; +static unsigned fx_devs = 0;
device_t get_node_pci(u32 nodeid, u32 fn) { @@ -719,7 +719,7 @@ static void amdfam10_domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -879,7 +879,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id==-1) { resource_t limitk_pri = 0; - for (i=0; i<sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { struct dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -1348,7 +1348,7 @@ static void sysconf_init(device_t dev) // first node
unsigned ht_c_index;
- for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { sysconf.ht_c_conf_bus[ht_c_index] = 0; }
@@ -1556,7 +1556,7 @@ static void cpu_bus_scan(device_t dev) devn = CONFIG_CDB+i; pbus = dev_mc->bus; #if CONFIG_CBB && (NODE_NUMS > 32) - if (i>=32) { + if (i >= 32) { busn--; devn-=32; pbus = pci_domain->link_list->next; diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 7c7065df..e73f80a 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -17,7 +17,7 @@ #define RAMINIT_H
#if 0 -#if CONFIG_DIMM_SUPPORT==0x0110 +#if CONFIG_DIMM_SUPPORT == 0x0110 //FBDIMM REG /* each channel can have 8 fbdimm */ #define DIMM_SOCKETS 8 diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 6d063ab..0e4c6bb 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -644,7 +644,7 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) struct sys_info *sysinfo = &sysinfo_car; struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
- for (j=0;j<DIMM_SOCKETS;j++) { + for (j = 0; j < DIMM_SOCKETS; j++) { pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff; pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff; } diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c index df3850b..0461323 100644 --- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c +++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c @@ -56,7 +56,7 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const int j; int index = 0; struct mem_controller *ctrl; - for (i=0;i<controllers; i++) { + for (i = 0; i < controllers; i++) { ctrl = &ctrl_a[i]; ctrl->node_id = i; ctrl->f0 = NODE_PCI(i, 0); @@ -70,7 +70,7 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const
ctrl->spd_switch_addr = spd_addr[index++];
- for (j=0; j < 8; j++) { + for (j = 0; j < 8; j++) { ctrl->spd_addr[j] = spd_addr[index++];
} diff --git a/src/northbridge/amd/amdht/AsPsNb.c b/src/northbridge/amd/amdht/AsPsNb.c index e34fa4c..90e78e0 100644 --- a/src/northbridge/amd/amdht/AsPsNb.c +++ b/src/northbridge/amd/amdht/AsPsNb.c @@ -43,13 +43,13 @@ u8 getMinNbCOF(void) numOfNode = getNumOfNodeNb();
/* go through each node for the minimum NbCOF (in multiple of CLKIN/2) */ - for (i=0; i < numOfNode; i++) + for (i = 0; i < numOfNode; i++) { /* stub function for APIC ID virtualization for large MP system later */ deviceId = translateNodeIdToDeviceIdNb(i);
- /* read all P-state spec registers for NbDid=1 */ - for (j=0; j < 5; j++) + /* read all P-state spec registers for NbDid = 1 */ + for (j = 0; j < 5; j++) { AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_4,PS_SPEC_REG+(j*PCI_REG_LEN)), &dtemp); /*F4x1E0 + j*4 */ /* get NbDid */ @@ -92,7 +92,7 @@ u8 getMinNbCOF(void) nbFid = nextNbFid; }
- /* add the base and convert to 100MHz divide by 2 if DID=1 */ + /* add the base and convert to 100MHz divide by 2 if DID = 1 */ if (nbDid) nbFid = (u8) (nbFid + 4); else diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index bfda13d..03bbe9c 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1807,7 +1807,7 @@ static void tuning(sMainData *pDat) /* For each node, invoke northbridge specific buffer tunings or * system specific customizations. */ - for (i=0; i < pDat->NodesDiscovered + 1; i++) + for (i = 0; i < pDat->NodesDiscovered + 1; i++) { if ((pDat->HtBlock->AMD_CB_CustomizeBuffers == NULL) || !pDat->HtBlock->AMD_CB_CustomizeBuffers(i)) diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index cbe90e0..0d0055b 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -352,11 +352,11 @@ static void enableRoutingTables(u8 node, cNorthBridge *nb) * @param[in] link = the link on that Node to examine * @param[in] *nb = this northbridge * @return true - The link has the following status - * linkCon=1, Link is connected - * InitComplete=1, Link initialization is complete - * NC=0, Link is coherent - * UniP-cLDT=0, Link is not Uniprocessor cLDT - * LinkConPend=0 Link connection is not pending + * linkCon = 1, Link is connected + * InitComplete = 1, Link initialization is complete + * NC = 0, Link is coherent + * UniP-cLDT = 0, Link is not Uniprocessor cLDT + * LinkConPend = 0 Link connection is not pending * false- The link has some other status * *****************************************************************************/ @@ -375,7 +375,7 @@ static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) /* FN0_98/A4/C4 = LDT Type Register */ AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType);
- /* Verify LinkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */ + /* Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */ return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT; #else return 0; @@ -612,7 +612,7 @@ static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) CPU_NB_FUNC_03, REG_NB_DOWNCORE_3X190), 3, 0, &leveling); - for (i=0; i<cores; i++) + for (i = 0; i < cores; i++) { if (leveling & ((u32) 1 << i)) { @@ -662,7 +662,7 @@ static u8 fam15GetNumCoresOnNode(u8 node, cNorthBridge *nb) CPU_NB_FUNC_03, REG_NB_DOWNCORE_3X190), 31, 0, &leveling); - for (i=0; i<cores; i++) + for (i = 0; i < cores; i++) { if (leveling & ((u32) 1 << i)) { @@ -1122,11 +1122,11 @@ static u8 readSbLink(cNorthBridge *nb) * @param[in] link = the Link on that node to examine * @param[in] *nb = this northbridge * @return = true - The link has the following status - * LinkCon=1, Link is connected - * InitComplete=1,Link initilization is complete - * NC=1, Link is coherent - * UniP-cLDT=0, Link is not Uniprocessor cLDT - * LinkConPend=0 Link connection is not pending + * LinkCon = 1, Link is connected + * InitComplete = 1,Link initilization is complete + * NC = 1, Link is coherent + * UniP-cLDT = 0, Link is not Uniprocessor cLDT + * LinkConPend = 0 Link connection is not pending * false- The link has some other status * * --------------------------------------------------------------------------------------- @@ -1143,7 +1143,7 @@ static BOOL verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb) /* FN0_98/A4/C4 = LDT Type Register */ AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType);
- /* Verify linkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */ + /* Verify linkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */ return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_NONCOHERENT; }
@@ -1922,7 +1922,7 @@ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge * CPU_HTNB_FUNC_00, REG_HT_TRAFFIC_DIST_0X164), 23, 16, &links01); - /* DstNode = 1, cHTPrbDistEn=1, cHTRspDistEn=1, cHTReqDistEn=1 */ + /* DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 */ temp = 0x0107; AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(0), makePCIBusFromNode(0), @@ -1939,7 +1939,7 @@ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge * CPU_HTNB_FUNC_00, REG_HT_TRAFFIC_DIST_0X164), 23, 16, &links10); - /* DstNode = 0, cHTPrbDistEn=1, cHTRspDistEn=1, cHTReqDistEn=1 */ + /* DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 */ temp = 0x0007; AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(1), makePCIBusFromNode(1), @@ -2088,13 +2088,13 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) makePCIDeviceFromNode(node), CPU_NB_FUNC_03, REG_NB_FIFOPTR_3XDC); - for (i=0; i < nb->maxLinks; i++) + for (i = 0; i < nb->maxLinks; i++) { temp = 0; if (nb->verifyLinkIsCoherent(node, i, nb)) { temp = 0x26; - ASSERT(i<3); + ASSERT(i < 3); AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp); } else @@ -2102,7 +2102,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) if (nb->verifyLinkIsNonCoherent(node, i, nb)) { temp = 0x25; - ASSERT(i<3); + ASSERT(i < 3); AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp); } } @@ -2142,7 +2142,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) * Errata 153 applies to JH-1, JH-2 and older. It is fixed in JH-3 * (and, one assumes, from there on). */ - for (i=0; i < (pDat->NodesDiscovered +1); i++) + for (i = 0; i < (pDat->NodesDiscovered +1); i++) { AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(i), makePCIBusFromNode(i), @@ -2158,7 +2158,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) } }
- for (i=0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++) + for (i = 0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++) { isOuter = FALSE; /* Check for outer node by scanning the config maps on node 0 for one @@ -2179,7 +2179,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) if (node == (u8)temp) { /* This is an outer node. Tune it appropriately. */ - for (j=0; j < nb->maxLinks; j++) + for (j = 0; j < nb->maxLinks; j++) { if (isErrata153) { @@ -2218,7 +2218,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) if (isErrata153) { /* Tuning for inner node coherent links */ - for (j=0; j < nb->maxLinks; j++) + for (j = 0; j < nb->maxLinks; j++) { if (nb->verifyLinkIsCoherent(node, j, nb)) { diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 992a85e..7e37d84 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -101,7 +101,7 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res) */ if ((basek+sizek)<1024) return;
- if (basek<1024) { + if (basek < 1024) { sizek -= 1024 - basek; basek = 1024; } @@ -158,29 +158,29 @@ static unsigned long acpi_fill_slit(unsigned long current) p += 8;
#if 0 - for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { if ((sysconf.pci1234[i]&1) !=1 ) continue; outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node } #endif
- for (i=0;i<nodes;i++) { - for (j=0;j<nodes; j++) { - if (i==j) { + for (i = 0; i < nodes; i++) { + for (j = 0; j < nodes; j++) { + if (i == j) { p[i*nodes+j] = 10; } else { #if 0 int k; u8 latency_factor = 0; int k_start, k_end; - if (i<j) { + if (i < j) { k_start = i; k_end = j; } else { k_start = j; k_end = i; } - for (k=k_start;k<=k_end; k++) { + for (k = k_start; k <= k_end; k++) { if (outer_node[k]) { latency_factor = 1; break; @@ -238,10 +238,10 @@ static void k8acpi_write_HT(void) { acpigen_write_name("HCLK"); acpigen_write_package(HC_POSSIBLE_NUM);
- for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { acpigen_write_dword(sysconf.pci1234[i]); } - for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x0); }
@@ -250,10 +250,10 @@ static void k8acpi_write_HT(void) { acpigen_write_name("HCDN"); acpigen_write_package(HC_POSSIBLE_NUM);
- for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { acpigen_write_dword(sysconf.hcdn[i]); } - for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x20202020); } acpigen_pop_len(); @@ -268,7 +268,7 @@ static void k8acpi_write_pci_data(int dlen, const char *name, int offset) {
acpigen_write_name(name); acpigen_write_package(dlen); - for (i=0; i<dlen; i++) { + for (i = 0; i < dlen; i++) { dword = pci_read_config32(dev, offset+i*4); acpigen_write_dword(dword); } diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 7e33feb..468e0db 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -139,7 +139,7 @@ static void disable_probes(void)
printk(BIOS_SPEW, "Disabling read/write/fill probes for UP... ");
- val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL); + val = pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL); val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C | HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P | HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P; @@ -193,7 +193,7 @@ static void enable_routing(u8 node) /* Enable routing table */ printk(BIOS_SPEW, "Enabling routing table for node %d", node);
- val=pci_read_config32(NODE_HT(node), 0x6c); + val = pci_read_config32(NODE_HT(node), 0x6c); val &= ~((1<<1)|(1<<0)); pci_write_config32(NODE_HT(node), 0x6c, val);
@@ -241,7 +241,7 @@ static void rename_temp_node(u8 node)
printk(BIOS_SPEW, "Renaming current temporary node to %d", node);
- val=pci_read_config32(NODE_HT(7), 0x60); + val = pci_read_config32(NODE_HT(7), 0x60); val &= (~7); /* clear low bits. */ val |= node; /* new node */ pci_write_config32(NODE_HT(7), 0x60, val); @@ -401,7 +401,7 @@ static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is fo uint8_t linkn; uint32_t val; val = 1; - for (linkn = 0; linkn<3; linkn++) { + for (linkn = 0; linkn < 3; linkn++) { uint8_t regpos; uint32_t reg; regpos = 0x98 + 0x20 * linkn; @@ -423,7 +423,7 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn)
if (((source &1)!=(dest &1)) #if CROSS_BAR_47_56 - && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here + && ( (source < 4)||(source>5) ) //(6,7) (7,6) should still be here //(6,5) (7,4) should be here #endif ){ @@ -453,7 +453,7 @@ static void opt_broadcast_rt_group(const u8 *conn, int num) { int i;
- for (i=0; i<num; i+=3) { + for (i = 0; i < num; i+=3) { opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]); } } @@ -470,7 +470,7 @@ static void opt_broadcast_rt_plus_group(const u8 *conn, int num) { int i;
- for (i=0; i<num; i+=3) { + for (i = 0; i < num; i+=3) { opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]); } } @@ -535,7 +535,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif #if !CROSS_BAR_47_56 u8 gateway; u8 diff; - if (source<dest) { + if (source < dest) { gateway = source + 2; } else { gateway = source - 2; @@ -562,14 +562,14 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif byte = val_s; byte = get_linkn_last_count(byte); if ((byte>>2)>1) { /* make sure not the corner*/ - if (source<dest) { + if (source < dest) { val_s-=link_connection(temp, source-2); /* -down*/ } else { #if CROSS_BAR_47_56 #if 0 - if (source==7) { + if (source == 7) { val_s-=link_connection(temp, 6); // for 7,2 via 5 - } else if (source==6){ + } else if (source == 6){ val_s-=link_connection(temp, 7); // for 6,3 via 4 } else #endif @@ -614,10 +614,10 @@ static void setup_row_indirect_group(const u8 *conn, int num) int i;
#if !CROSS_BAR_47_56 - for (i=0; i<num; i+=2) { + for (i = 0; i < num; i+=2) { setup_row_indirect(conn[i], conn[i+1]); #else - for (i=0; i<num; i+=4) { + for (i = 0; i < num; i+=4) { setup_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]); #endif
@@ -641,10 +641,10 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num) int i;
#if !CROSS_BAR_47_56 - for (i=0; i<num; i+=2) { + for (i = 0; i < num; i+=2) { setup_remote_row_indirect(conn[i], conn[i+1]); #else - for (i=0; i<num; i+=4) { + for (i = 0; i < num; i+=4) { setup_remote_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]); #endif } @@ -668,7 +668,7 @@ static int optimize_connection_group(const u8 *opt_conn, int num) { int needs_reset = 0; int i; - for (i=0; i<num; i+=2) { + for (i = 0; i < num; i+=2) { needs_reset = optimize_connection( NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])), NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) ); @@ -689,7 +689,7 @@ static unsigned setup_smp2(void)
val = get_row(0,0); byte = (val>>16) & 0xfe; - if (byte<0x2) { /* no coherent connection so get out.*/ + if (byte < 0x2) { /* no coherent connection so get out.*/ nodes = 1; return nodes; } @@ -760,7 +760,7 @@ static unsigned setup_smp4(void) u8 byte; uint32_t val;
- nodes=4; + nodes = 4;
/* Setup and check temporary connection from Node 0 to Node 2 */ val = get_row(0,0); @@ -931,7 +931,7 @@ static unsigned setup_smp6(void) u8 byte; uint32_t val;
- nodes=6; + nodes = 6;
/* Setup and check temporary connection from Node 0 to Node 4 through 2*/ val = get_row(2,2); @@ -975,7 +975,7 @@ static unsigned setup_smp6(void)
setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1));
- for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte,byte+2); } verify_connection(7); @@ -1003,7 +1003,7 @@ static unsigned setup_smp6(void) enable_routing(4);
setup_temp_row(0,1); - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte+1,byte+3); } verify_connection(7); @@ -1115,7 +1115,7 @@ static unsigned setup_smp6(void) /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) * It will be done by clear_dead_links */ - for (byte=0; byte<4; byte++) { + for (byte = 0; byte < 4; byte++) { clear_temp_row(byte); } #endif @@ -1134,7 +1134,7 @@ static unsigned setup_smp8(void) u8 byte; uint32_t val;
- nodes=8; + nodes = 8;
/* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */ val = get_row(4,4); @@ -1203,7 +1203,7 @@ static unsigned setup_smp8(void)
setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1));
- for (byte=0; byte<6; byte+=2) { + for (byte = 0; byte < 6; byte+=2) { setup_temp_row(byte,byte+2); } verify_connection(7); @@ -1241,7 +1241,7 @@ static unsigned setup_smp8(void) setup_row_direct(5, 6, byte);
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte+1,byte+3); } setup_temp_row(5,6); @@ -1262,7 +1262,7 @@ static unsigned setup_smp8(void) setup_row_direct(5, 6, byte); #if 0 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte+1,byte+3); } #endif @@ -1282,7 +1282,7 @@ static unsigned setup_smp8(void)
#if !CROSS_BAR_47_56 setup_temp_row(0,1); - for (byte=0; byte<6; byte+=2) { + for (byte = 0; byte < 6; byte+=2) { setup_temp_row(byte+1,byte+3); }
@@ -1302,7 +1302,7 @@ static unsigned setup_smp8(void) setup_row_direct(4, 7, byte);
/* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/ - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte,byte+2); }
@@ -1327,7 +1327,7 @@ static unsigned setup_smp8(void) setup_row_direct(5, 7, byte);
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte+1,byte+3); }
@@ -1511,7 +1511,7 @@ static unsigned verify_mp_capabilities(unsigned nodes)
mask = 0x06; /* BigMPCap */
- for (node=0; node<nodes; node++) { + for (node = 0; node < nodes; node++) { mask &= pci_read_config32(NODE_MC(node), 0xe8); }
@@ -1542,7 +1542,7 @@ static void clear_dead_routes(unsigned nodes) int last_row; int node, row; #if CONFIG_MAX_PHYSICAL_CPUS == 8 - if (nodes==8) return;/* don't touch (7,7)*/ + if (nodes == 8) return;/* don't touch (7,7)*/ #endif last_row = nodes; if (nodes == 1) { @@ -1555,9 +1555,9 @@ static void clear_dead_routes(unsigned nodes) }
/* Update the local row */ - for ( node=0; node<nodes; node++) { + for ( node = 0; node < nodes; node++) { uint32_t val = 0; - for (row =0; row<nodes; row++) { + for (row =0; row < nodes; row++) { val |= get_row(node, row); } fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101); @@ -1571,7 +1571,7 @@ static unsigned verify_dualcore(unsigned nodes) unsigned node, totalcpus, tmp;
totalcpus = 0; - for (node=0; node<nodes; node++) { + for (node = 0; node < nodes; node++) { tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ; totalcpus += (tmp + 1); } @@ -1626,7 +1626,7 @@ static void coherent_ht_finalize(unsigned nodes) /* Only respond to real CPU pci configuration cycles * and optimize the HT settings */ - val=pci_read_config32(dev, HT_TRANSACTION_CONTROL); + val = pci_read_config32(dev, HT_TRANSACTION_CONTROL); val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) | (HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) | (HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT)); diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index 18fc858..650b509 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -71,7 +71,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) int j; printk(BIOS_DEBUG, "\n%02x:",i); val = pci_read_config32_index_wait(dev, index_reg, i); - for (j=0;j<4;j++) { + for (j = 0; j < 4; j++) { printk(BIOS_DEBUG, " %02x", val & 0xff); val >>= 8; } @@ -211,7 +211,7 @@ static inline void dump_io_resources(unsigned port) int i; udelay(2000); printk(BIOS_DEBUG, "%04x:\n", port); - for (i=0;i<256;i++) { + for (i = 0; i < 256; i++) { uint8_t val; if ((i & 0x0f) == 0) { printk(BIOS_DEBUG, "%02x:", i); @@ -229,7 +229,7 @@ static inline void dump_mem(unsigned start, unsigned end) { unsigned i; printk(BIOS_DEBUG, "dump_mem:"); - for (i=start;i<end;i++) { + for (i = start; i < end; i++) { if ((i & 0xf)==0) { printk(BIOS_DEBUG, "\n%08x:", i); } diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index d07da2a..940a00c 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -64,7 +64,7 @@ static void enumerate_ht_chain(void) pci_devfn_t devx;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. + if (next_unitid >= 0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. if (!end_used) { next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index ce039af..0440031 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -537,7 +537,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
if (sysinfo->nodes == 1) return; // in case only one CPU installed
- for (i=1; i<sysinfo->nodes; i++) { + for (i = 1; i < sysinfo->nodes; i++) { /* Skip everything if I don't have any memory on this controller */ if (sysinfo->mem_trained[i]==0x00) continue;
@@ -564,7 +564,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) i%=sysinfo->nodes; }
- for (i=0; i<sysinfo->nodes; i++) { + for (i = 0; i < sysinfo->nodes; i++) { printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); switch(sysinfo->mem_trained[i]) { case 0: //don't need train diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index 9cf4083..a3517c8 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -51,7 +51,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link) dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; #if 0 - printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + printk(BIOS_DEBUG, "node.link = bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); #endif @@ -211,7 +211,7 @@ void get_sblk_pci1234(void)
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
- for (j=0;j<4;j++) { + for (j = 0; j < 4; j++) { uint32_t dwordx; dwordx = pci_read_config32(dev, 0xe0 + j*4); dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */ @@ -225,7 +225,7 @@ void get_sblk_pci1234(void) /* We need to find out the number of HC * for exact match */ - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; @@ -234,7 +234,7 @@ void get_sblk_pci1234(void) }
/* For 0xff0 match or same node */ - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; @@ -244,7 +244,7 @@ void get_sblk_pci1234(void) } }
- for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((sysconf.pci1234[i] & 1) != 1) { sysconf.pci1234[i] = 0; sysconf.hcdn[i] = 0x20202020; diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index bc50b66..fe51441 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -118,7 +118,7 @@ static uint16_t ht_read_freq_cap(pci_devfn_t dev, uint8_t pos) uint32_t id;
freq_cap = pci_read_config16(dev, pos); - printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap); + printk(BIOS_SPEW, "pos = 0x%x, unfiltered freq_cap = 0x%x\n", pos, freq_cap); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
id = pci_read_config32(dev, 0); @@ -148,7 +148,7 @@ static uint16_t ht_read_freq_cap(pci_devfn_t dev, uint8_t pos) #endif }
- printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap); + printk(BIOS_SPEW, "pos = 0x%x, filtered freq_cap = 0x%x\n", pos, freq_cap);
#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 freq_cap &= 0x3f; @@ -221,7 +221,7 @@ static int ht_optimize_link( /* Get the frequency capabilities */ freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1)); freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2)); - printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\n", freq_cap1, freq_cap2); + printk(BIOS_SPEW, "freq_cap1 = 0x%x, freq_cap2 = 0x%x\n", freq_cap1, freq_cap2);
/* Calculate the highest possible frequency */ freq = log2(freq_cap1 & freq_cap2); @@ -230,11 +230,11 @@ static int ht_optimize_link( old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset); + printk(BIOS_SPEW, "dev1 old_freq = 0x%x, freq = 0x%x, needs_reset = 0x%0x\n", old_freq, freq, needs_reset); old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset); + printk(BIOS_SPEW, "dev2 old_freq = 0x%x, freq = 0x%x, needs_reset = 0x%0x\n", old_freq, freq, needs_reset);
/* Set the Calculated link frequency */ pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq); @@ -243,45 +243,45 @@ static int ht_optimize_link( /* Get the width capabilities */ width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1)); width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2)); - printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\n", width_cap1, width_cap2); + printk(BIOS_SPEW, "width_cap1 = 0x%x, width_cap2 = 0x%x\n", width_cap1, width_cap2);
/* Calculate dev1's input width */ ln_width1 = link_width_to_pow2[width_cap1 & 7]; ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7]; - printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2); + printk(BIOS_SPEW, "dev1 input ln_width1 = 0x%x, ln_width2 = 0x%x\n", ln_width1, ln_width2); if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width = pow2_to_link_width[ln_width1]; - printk(BIOS_SPEW, "dev1 input width=0x%x\n", width); + printk(BIOS_SPEW, "dev1 input width = 0x%x\n", width); /* Calculate dev1's output width */ ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7]; ln_width2 = link_width_to_pow2[width_cap2 & 7]; - printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2); + printk(BIOS_SPEW, "dev1 output ln_width1 = 0x%x, ln_width2 = 0x%x\n", ln_width1, ln_width2); if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width |= pow2_to_link_width[ln_width1] << 4; - printk(BIOS_SPEW, "dev1 input|output width=0x%x\n", width); + printk(BIOS_SPEW, "dev1 input|output width = 0x%x\n", width);
/* See if I am changing dev1's width */ old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1); old_width &= 0x77; needs_reset |= old_width != width; - printk(BIOS_SPEW, "old dev1 input|output width=0x%x\n", width); + printk(BIOS_SPEW, "old dev1 input|output width = 0x%x\n", width);
/* Set dev1's widths */ pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width);
/* Calculate dev2's width */ width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); - printk(BIOS_SPEW, "dev2 input|output width=0x%x\n", width); + printk(BIOS_SPEW, "dev2 input|output width = 0x%x\n", width);
/* See if I am changing dev2's width */ old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1); old_width &= 0x77; needs_reset |= old_width != width; - printk(BIOS_SPEW, "old dev2 input|output width=0x%x\n", width); + printk(BIOS_SPEW, "old dev2 input|output width = 0x%x\n", width);
/* Set dev2's widths */ pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width); @@ -448,7 +448,7 @@ end_of_chain: ; #if CONFIG_RAMINIT_SYSINFO // Here need to change the dev in the array int i; - for (i=0;i<sysinfo->link_pair_num;i++) + for (i = 0; i < sysinfo->link_pair_num; i++) { struct link_pair_st *link_pair = &sysinfo->link_pair[i]; if (link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) { @@ -659,8 +659,8 @@ static int ht_setup_chains(uint8_t ht_c_num) reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
//We need setup 0x94, 0xb4, and 0xd4 according to the reg - devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19 - regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4; + devpos = ((reg & 0xf0)>>4)+0x18; // nodeid;it will decide 0x18 or 0x19 + regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n;it will decide 0x94 or 0xb4, 0x0xd4; busn = (reg & 0xff0000)>>16;
dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ; @@ -712,7 +712,7 @@ static int ht_setup_chains_x(void)
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); - /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */ + /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn = 0x3f+1 */ print_linkn_in("SBLink=", ((reg>>8) & 3) ); #if CONFIG_RAMINIT_SYSINFO sysinfo->sblk = (reg>>8) & 3; @@ -722,7 +722,7 @@ static int ht_setup_chains_x(void) tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24); pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg);
- next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/ + next_busn = 0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
#if CONFIG_K8_ALLOCATE_IO_RANGE /* io range allocation */ @@ -734,7 +734,7 @@ static int ht_setup_chains_x(void) #endif
/* clean others */ - for (ht_c_num=1;ht_c_num<4; ht_c_num++) { + for (ht_c_num = 1;ht_c_num < 4; ht_c_num++) { pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
#if CONFIG_K8_ALLOCATE_IO_RANGE @@ -744,11 +744,11 @@ static int ht_setup_chains_x(void) #endif }
- for (nodeid=0; nodeid<nodes; nodeid++) { + for (nodeid = 0; nodeid < nodes; nodeid++) { pci_devfn_t dev; uint8_t linkn; dev = PCI_DEV(0, 0x18+nodeid,0); - for (linkn = 0; linkn<3; linkn++) { + for (linkn = 0; linkn < 3; linkn++) { unsigned regpos; regpos = 0x98 + 0x20 * linkn; reg = pci_read_config32(dev, regpos); @@ -756,7 +756,7 @@ static int ht_setup_chains_x(void) print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf)); tempreg = 3 | (nodeid <<4) | (linkn<<8); /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */ - for (ht_c_num=0;ht_c_num<4; ht_c_num++) { + for (ht_c_num = 0;ht_c_num < 4; ht_c_num++) { reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); if (((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/ break; @@ -783,7 +783,7 @@ static int ht_setup_chains_x(void) } /*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
- for (nodeid = 1; nodeid<nodes; nodeid++) { + for (nodeid = 1; nodeid < nodes; nodeid++) { int i; pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,1); @@ -812,8 +812,8 @@ static int ht_setup_chains_x(void) }
/* recount ht_c_num*/ - uint8_t i=0; - for (ht_c_num=0;ht_c_num<4; ht_c_num++) { + uint8_t i = 0; + for (ht_c_num = 0;ht_c_num < 4; ht_c_num++) { reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); if (((reg & 0xf) != 0x0)) { i++; @@ -840,15 +840,15 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo) unsigned link_pair_num = sysinfo->link_pair_num;
printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n"); - printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num); - for (i=0; i< link_pair_num; i++) { + printk(BIOS_SPEW, "sysinfo->link_pair_num = 0x%x\n", link_pair_num); + for (i = 0; i< link_pair_num; i++) { struct link_pair_st *link_pair= &sysinfo->link_pair[i]; reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs); - printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed); + printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed = 0x%x\n", i, reset_needed); }
reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num); - printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\n", reset_needed); + printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed = 0x%x\n", reset_needed);
return reset_needed;
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index d80c565..2f0df22 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -42,7 +42,7 @@ struct amdk8_sysconf_t sysconf; #define MAX_FX_DEVS 8 static device_t __f0_dev[MAX_FX_DEVS]; static device_t __f1_dev[MAX_FX_DEVS]; -static unsigned fx_devs=0; +static unsigned fx_devs = 0;
static void get_fx_devs(void) { @@ -697,7 +697,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id==-1) { u32 limitk_pri = 0; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { u32 base, limit; unsigned base_k, limit_k; base = f1_read_config32(0x40 + (i << 3)); @@ -738,7 +738,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id)
hole_sizek = (4*1024*1024) - hole_startk;
- for (i=7;i>node_id;i--) { + for (i = 7; i>node_id; i--) {
base = f1_read_config32(0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -775,7 +775,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id)
carry_over = (4*1024*1024) - hole_startk;
- for (i=7;i>node_id;i--) { + for (i = 7; i>node_id; i--) {
base = f1_read_config32(0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -962,7 +962,7 @@ static void amdk8_domain_set_resources(device_t dev)
#if CONFIG_GFXUMA - printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + printk(BIOS_DEBUG, "node %d : uma_memory_base/1024 = 0x%08llx, mmio_basek = 0x%08lx, basek = 0x%08x, limitk = 0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); if ((uma_memory_base >> 10) < mmio_basek) printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i); #else @@ -1222,7 +1222,7 @@ static void cpu_bus_scan(device_t dev) if (e0_later_single_core) { printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
- j=1; + j = 1; }
if (siblings > j ) { diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index aab9fa7..bcf2e68 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -748,7 +748,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index) { static const unsigned cs_map_aa[] = { - /* (row=12, col=8)(14, 12) ---> (0, 0) (2, 4) */ + /* (row = 12, col = 8)(14, 12) ---> (0, 0) (2, 4) */ 0, 1, 3, 6, 0, 0, 2, 4, 7, 9, 0, 0, 5, 8,10, @@ -974,7 +974,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) else { csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode]; if (is_dual_channel(ctrl)) { - if ( (bits==3) && (common_cs_mode > 8)) { + if ( (bits == 3) && (common_cs_mode > 8)) { // printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\n"); return 0; } @@ -1223,7 +1223,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 5, /* *Physical Banks */ 6, /* *Module Data Width low */ 7, /* *Module Data Width high */ - 9, /* *Cycle time at highest CAS Latency CL=X */ + 9, /* *Cycle time at highest CAS Latency CL = X */ 11, /* *SDRAM Type */ 13, /* *SDRAM Width */ 17, /* *Logical Banks */ @@ -1390,7 +1390,7 @@ static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_
/* Following table comes directly from BKDG (unbuffered DIMM support) - [Y][X] Y = ch0_0, ch1_0, ch0_1, ch1_1 1=present 0=empty + [Y][X] Y = ch0_0, ch1_0, ch0_1, ch1_1 1 = present 0 = empty X uses same layout but 1 means double rank 0 is single rank/empty
Following tables come from BKDG the ch{0_0,1_0,0_1,1_1} maps to @@ -1674,7 +1674,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * #if 0 /* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 and higher speeds with certain DIMM loadings ---- cheating???*/ if (!is_cpu_pre_e0()) { - if (min_cycle_time==0x50) { + if (min_cycle_time == 0x50) { value |= 1<<31; } } @@ -1927,7 +1927,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa
dimm = 1<<(DCL_x4DIMM_SHIFT+i); #if CONFIG_QRANK_DIMM_SUPPORT - if (rank==4) { + if (rank == 4) { dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2); } #endif @@ -2239,7 +2239,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,
carry_over = (4*1024*1024) - hole_startk;
- for (ii=controllers - 1;ii>i;ii--) { + for (ii = controllers - 1; ii>i; ii--) { base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; @@ -2294,7 +2294,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) * we need to decrease it. */ uint32_t basek_pri; - for (i=0; i<controllers; i++) { + for (i = 0; i < controllers; i++) { uint32_t base; unsigned base_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); @@ -2315,7 +2315,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) printk(BIOS_SPEW, "Handling memory hole at 0x%08x (adjusted)\n", hole_startk); #endif /* Find node number that needs the memory hole configured */ - for (i=0; i<controllers; i++) { + for (i = 0; i < controllers; i++) { uint32_t base, limit; unsigned base_k, limit_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); @@ -2495,7 +2495,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, int i; int j; struct mem_controller *ctrl; - for (i=0;i<controllers; i++) { + for (i = 0; i < controllers; i++) { ctrl = &ctrl_a[i]; ctrl->node_id = i; ctrl->f0 = PCI_DEV(0, 0x18+i, 0); @@ -2505,7 +2505,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
if (spd_addr == (void *)0) continue;
- for (j=0;j<DIMM_SOCKETS;j++) { + for (j = 0; j < DIMM_SOCKETS; j++) { ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j]; ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j]; } diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 67f3433..649c966 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -932,7 +932,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl, struct mem_info *meminfo) { static const uint8_t cs_map_aaa[24] = { - /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */ + /* (bank = 2, row = 13, col = 9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */ //Bank2 0, 1, 3, 0, 2, 6, @@ -1441,7 +1441,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i * Keep them at the end to see other mismatches (if any). */ 18, /* *Supported CAS Latencies */ - 9, /* *Cycle time at highest CAS Latency CL=X */ + 9, /* *Cycle time at highest CAS Latency CL = X */ 23, /* *Cycle time at CAS Latency (CLX - 1) */ 25, /* *Cycle time at CAS Latency (CLX - 2) */ }; @@ -2267,7 +2267,7 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, mask_single_rank |= 1<<i; }
- if (meminfo->sz[i].col==10) { + if (meminfo->sz[i].col == 10) { mask_page_1k |= 1<<i; }
@@ -2278,17 +2278,17 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, rank = meminfo->sz[i].rank; #endif
- if (value==4) { + if (value == 4) { mask_x4 |= (1<<i); #if CONFIG_QRANK_DIMM_SUPPORT - if (rank==4) { + if (rank == 4) { mask_x4 |= 1<<(i+2); } #endif - } else if (value==16) { + } else if (value == 16) { mask_x16 |= (1<<i); #if CONFIG_QRANK_DIMM_SUPPORT - if (rank==4) { + if (rank == 4) { mask_x16 |= 1<<(i+2); } #endif @@ -2528,7 +2528,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * unsigned SlowAccessMode = 0; #endif
-#if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */ +#if CONFIG_DIMM_SUPPORT == 0x0104 /* DDR2 and REG */ long dimm_mask = meminfo->dimm_mask & 0x0f; /* for REG DIMM */ dword = 0x00111222; @@ -2553,7 +2553,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
#endif
-#if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */ +#if CONFIG_DIMM_SUPPORT == 0x0204 /* DDR2 and SO-DIMM, S1G1 */ dword = 0x00111222; dwordx = 0x002F2F00;
@@ -2593,7 +2593,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * } #endif
-#if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ +#if CONFIG_DIMM_SUPPORT == 0x0004 /* DDR2 and unbuffered */ long dimm_mask = meminfo->dimm_mask & 0x0f; /* for UNBUF DIMM */ dword = 0x00111222; @@ -2707,7 +2707,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * static void set_RDqsEn(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { -#if CONFIG_CPU_SOCKET_TYPE==0x10 +#if CONFIG_CPU_SOCKET_TYPE == 0x10 //only need to set for reg and x8 uint32_t dch;
@@ -2844,7 +2844,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, activate_spd_rom(ctrl); meminfo->dimm_mask = spd_detect_dimms(ctrl);
- printk_raminit("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("sdram_set_spd_registers: dimm_mask = 0x%x\n", meminfo->dimm_mask);
if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1))) { @@ -2852,24 +2852,24 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, return; } meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo); - printk_raminit("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_enable_2channels: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err;
meminfo->dimm_mask = spd_set_ram_size(ctrl, meminfo); - printk_raminit("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_ram_size: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err;
meminfo->dimm_mask = spd_handle_unbuffered_dimms(ctrl, meminfo); - printk_raminit("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_handle_unbuffered_dimms: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err;
result = spd_set_memclk(ctrl, meminfo); param = result.param; meminfo->dimm_mask = result.dimm_mask; - printk_raminit("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_memclk: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err;
@@ -2881,7 +2881,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor);
meminfo->dimm_mask = spd_set_dram_timing(ctrl, ¶mx, meminfo); - printk_raminit("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_dram_timing: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err;
@@ -2911,7 +2911,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,
carry_over = (4*1024*1024) - hole_startk;
- for (ii=controllers - 1;ii>i;ii--) { + for (ii = controllers - 1; ii>i; ii--) { base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; @@ -2966,7 +2966,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) /* We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some */ uint32_t basek_pri; - for (i=0; i<controllers; i++) { + for (i = 0; i < controllers; i++) { uint32_t base; unsigned base_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); @@ -2985,7 +2985,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk); #endif /* find node index that need do set hole */ - for (i=0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { uint32_t base, limit; unsigned base_k, limit_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); @@ -3038,7 +3038,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
/* if no memory installed, disabled the interface */ - if (sysinfo->meminfo[i].dimm_mask==0x00){ + if (sysinfo->meminfo[i].dimm_mask == 0x00){ dch |= DCH_DisDramInterface; pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
@@ -3108,7 +3108,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, if (!sysinfo->ctrl_present[ i ]) continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
printk(BIOS_DEBUG, "Initializing memory: "); int loops = 0; @@ -3136,7 +3136,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2); print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2);
- if (tsc.lo<tsc0[i].lo) { + if (tsc.lo < tsc0[i].lo) { tsc.hi--; } tsc.lo -= tsc0[i].lo; @@ -3176,7 +3176,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, continue;
/* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
sysinfo->mem_trained[i] = 0x80; // mem need to be trained @@ -3226,7 +3226,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, int i; int j; struct mem_controller *ctrl; - for (i=0;i<controllers; i++) { + for (i = 0; i < controllers; i++) { ctrl = &ctrl_a[i]; ctrl->node_id = i; ctrl->f0 = PCI_DEV(0, 0x18+i, 0); @@ -3236,7 +3236,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
if (spd_addr == (void *)0) continue;
- for (j=0;j<DIMM_SOCKETS;j++) { + for (j = 0; j < DIMM_SOCKETS; j++) { ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j]; ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j]; } diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 9f0b8db..b0d3ace 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -60,7 +60,7 @@ static void fill_mem_cs_sysinfo(unsigned nodeid, const struct mem_controller *ct int i; sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid<<3));
- for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { sysinfo->cs_base[nodeid*8+i] = pci_read_config32(ctrl->f2, 0x40 + (i<<2)); }
@@ -197,7 +197,7 @@ static void WriteLNTestPattern(unsigned addr_lo, uint8_t *buf_a, unsigned line_n static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b) { uint8_t *buf; - if (p==1) { buf = buf_b; } + if (p == 1) { buf = buf_b; } else { buf = buf_a; }
set_FSBASE (addr>>24); @@ -243,7 +243,7 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned unsigned result = DQS_FAIL;
if (Pass == DQS_FIRST_PASS) { - if (pattern==1) { + if (pattern == 1) { test_buf = (uint32_t *)TestPattern1; } else { @@ -291,7 +291,7 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned }
if (Pass == DQS_SECOND_PASS) { // second pass need to be inverted - if (result==DQS_PASS) { + if (result == DQS_PASS) { result = DQS_FAIL; } else { @@ -437,14 +437,14 @@ static void InitDQSPos4RcvrEn(const struct mem_controller *ctrl) uint32_t dword;
dword = 0x00000000; - for (i=1; i<=3; i++) { + for (i = 1; i <= 3; i++) { /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x01-0x03, 0x21-0x23) to 0x00 for all bytes */ pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); }
dword = 0x2f2f2f2f; - for (i=5; i<=7; i++) { + for (i = 5; i <= 7; i++) { /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x05-0x07, 0x25-0x27) to 0x2f for all bytes */ pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); @@ -554,14 +554,14 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st // SetupRcvrPattern buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (0xfffffff0)); buf_b = buf_a + 128; //?? - if (Pass==DQS_FIRST_PASS) { - for (i=0;i<16;i++) { + if (Pass == DQS_FIRST_PASS) { + for (i = 0; i < 16; i++) { *((uint32_t *)(buf_a + i*4)) = TestPattern0[i]; *((uint32_t *)(buf_b + i*4)) = TestPattern1[i]; } } else { - for (i=0;i<16;i++) { + for (i = 0; i < 16; i++) { *((uint32_t *)(buf_a + i*4)) = TestPattern2[i]; *((uint32_t *)(buf_b + i*4)) = TestPattern2[i]; } @@ -841,7 +841,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st printk(BIOS_DEBUG, " CTLRMaxDelay=%02x\n", CTLRMaxDelay); #endif
- return (CTLRMaxDelay==0xae)?1:0; + return (CTLRMaxDelay == 0xae)?1:0;
}
@@ -879,13 +879,13 @@ static void SetDQSDelayAllCSR(const struct mem_controller *ctrl, unsigned channe
dword = 0; dqs_delay &= 0xff; - for (i=0;i<4;i++) { + for (i = 0; i < 4; i++) { dword |= dqs_delay<<(i*8); }
index = 1 + channel * 0x20 + direction * 4;
- for (i=0; i<2; i++) { + for (i = 0; i < 2; i++) { pci_write_config32_index_wait(ctrl->f2, 0x98, index + i, dword); }
@@ -1056,7 +1056,7 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign }
bytelane = 0; - for (i=0;i<9*64/4;i++) { + for (i = 0; i < 9*64/4; i++) { __asm__ volatile ( "movl %%fs:(%1), %0\n\t" :"=b"(value): "a" (addr_lo) @@ -1066,7 +1066,7 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign print_debug_dqs_pair("\t\t\t\t\t\ttest_buf= ", (unsigned)test_buf, " value = ", value_test, 7); print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ",addr_lo, " value = ", value, 7);
- for (j=0;j<4*8;j+=8) { + for (j = 0; j < 4*8; j+=8) { if (((value>>j)&0xff) != ((value_test>>j)& 0xff)) { bitmap &= ~(1<<bytelane); } @@ -1116,8 +1116,8 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
printk(BIOS_DEBUG, "TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW);
- for (DQSDelay=0; DQSDelay<48; DQSDelay++) { - MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS) + for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) { + MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff = All positions passing (1= PASS) }
for (ChipSel = 0; ChipSel < 8; ChipSel++) { //logical register chipselects 0..7 @@ -1150,7 +1150,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", Pattern, 5); ReadDQSTestPattern(TestAddr<<8, Pattern); print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); - MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr<<8, Pattern, buf_a); //0: fail, 1=pass + MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr<<8, Pattern, buf_a); //0: fail, 1 = pass print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); SetTargetWTIO(TestAddr); FlushDQSTestPattern(TestAddr<<8, Pattern); @@ -1166,7 +1166,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, RnkDlySeqPassMax = 0; RnkDlyFilterMax = 0; RnkDlyFilterMin = 0; - for (DQSDelay=0; DQSDelay<48; DQSDelay++) { + for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) { if (MutualCSPassW[DQSDelay] & (1<<ByteLane)) {
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 321 DQSDelay ", DQSDelay, 5); @@ -1373,13 +1373,13 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in
if (is_Width128){ pattern = 1; - for (i=0;i<16*18;i++) { + for (i = 0; i < 16*18; i++) { *((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i]; } } else { pattern = 0; - for (i=0; i<16*9;i++) { + for (i = 0; i < 16*9; i++) { *((uint32_t *)(buf_a + i*4)) = TestPatternJD1a[i]; }
@@ -1397,7 +1397,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in channel = 1; }
- while ( (channel<2) && (!Errors)) { + while ( (channel < 2) && (!Errors)) { print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1); for (DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) { unsigned err; @@ -1496,11 +1496,11 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info ByteLane = 8;
for (channel = 0; channel < 2; channel++) { - for (i=0;i<2;i++) { + for (i = 0; i < 2; i++) { Direction = direction[i]; lane0 = 4; lane1 = 5; ratio = 0; dqs_delay = CalcEccDQSPos(channel, lane0, lane1, ratio, Direction, dqs_delay_a); - print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2); + print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2); SetDQSDelayCSR(ctrl, channel, ByteLane, Direction, dqs_delay); save_dqs_delay(channel, ByteLane, Direction, dqs_delay_a, dqs_delay); } @@ -1546,7 +1546,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl continue;
/* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
uint32_t dword;
@@ -1568,7 +1568,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2);
dword = tsc1[i].lo + tsc0[i].lo; - if ((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) { + if ((dword < tsc1[i].lo) || (dword < tsc0[i].lo)) { tsc1[i].hi++; } tsc1[i].lo = dword; @@ -1583,7 +1583,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl continue;
/* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
if (!cpu_f0_f1[i]) continue;
@@ -1591,7 +1591,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl
do { tsc = rdtsc(); - } while ((tsc1[i].hi>tsc.hi) || ((tsc1[i].hi==tsc.hi) && (tsc1[i].lo>tsc.lo))); + } while ((tsc1[i].hi>tsc.hi) || ((tsc1[i].hi == tsc.hi) && (tsc1[i].lo>tsc.lo)));
print_debug_dqs_tsc("end : tsc ", i, tsc.hi, tsc.lo, 2); } @@ -1661,8 +1661,8 @@ static unsigned int range_to_mtrr(unsigned int reg, #if CONFIG_MEM_TRAIN_SEQ != 1 printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", reg, range_startk >>10, sizek >> 10, - (type==MTRR_TYPE_UNCACHEABLE)?"UC": - ((type==MTRR_TYPE_WRBACK)?"WB":"Other") + (type == MTRR_TYPE_UNCACHEABLE)?"UC": + ((type == MTRR_TYPE_WRBACK)?"WB":"Other") ); #endif set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits); @@ -1737,7 +1737,7 @@ static void clear_mtrr_dqs(unsigned tom2_k) wrmsr(0x258, msr);
//[1M, TOM) - for (i=0x204;i<0x210;i++) { + for (i = 0x204; i < 0x210; i++) { wrmsr(i, msr); }
@@ -1890,7 +1890,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc continue;
/* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
fill_mem_cs_sysinfo(i, ctrl+i, sysinfo); } @@ -1901,7 +1901,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc continue;
/* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i); if (train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; @@ -1919,7 +1919,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc continue;
/* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i); if (train_DqsPos(ctrl+i, sysinfo)) goto out; @@ -1932,7 +1932,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc continue;
/* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i); if (train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; @@ -1948,7 +1948,7 @@ out: clear_mtrr_dqs(sysinfo->tom2_k);
- for (i=0;i<5;i++) { + for (i = 0; i < 5; i++) { print_debug_dqs_tsc_x("DQS Training:tsc", i, tsc[i].hi, tsc[i].lo); }
@@ -2021,7 +2021,7 @@ out: #endif
if (v) { - for (ii=0;ii<4;ii++) { + for (ii = 0; ii < 4; ii++) { print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); } } diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h index 61b2b2b..b169967 100644 --- a/src/northbridge/amd/amdmct/mct/mct.h +++ b/src/northbridge/amd/amdmct/mct/mct.h @@ -23,16 +23,16 @@ #define PT_M2 1 #define PT_S1 2
-#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/ -#define J_MAX 4 /* j loop constraint. 4=CL 6.0 T*/ -#define K_MIN 1 /* k loop constraint. 1=200 MHz*/ -#define K_MAX 4 /* k loop constraint. 9=400 MHz*/ -#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/ -#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/ - -#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/ +#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/ +#define J_MAX 4 /* j loop constraint. 4 = CL 6.0 T*/ +#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/ +#define K_MAX 4 /* k loop constraint. 9 = 400 MHz*/ +#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/ +#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/ + +#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/ /* memory initialization (ecc and check-bits).*/ - /* 1=40 ns/64 bytes.*/ + /* 1 = 40 ns/64 bytes.*/ #define FirstPass 1 /* First pass through RcvEn training*/ #define SecondPass 2 /* Second pass through Rcven training*/
@@ -208,7 +208,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* SPD address of..MB2_CS_L[0,1]*/ /* SPD address of..MA3_CS_L[0,1]*/ /* SPD address of..MB3_CS_L[0,1]*/ - u16 DIMMPresent; /* For each bit n 0..7, 1=DIMM n is present. + u16 DIMMPresent; /* For each bit n 0..7, 1 = DIMM n is present. DIMM# Select Signal 0 MA0_CS_L[0,1] 1 MB0_CS_L[0,1] @@ -218,14 +218,14 @@ struct DCTStatStruc { /* A per Node structure*/ 5 MB2_CS_L[0,1] 6 MA3_CS_L[0,1] 7 MB3_CS_L[0,1]*/ - u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/ - u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/ - u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/ - u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/ - u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/ - u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/ - u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/ - u16 DIMM1Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/ + u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/ + u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/ + u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/ + u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/ + u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/ + u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/ + u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/ + u16 DIMM1Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/ u8 MAload[2]; /* Number of devices loading MAA bus*/ /* Number of devices loading MAB bus*/ u8 MAdimms[2]; /* Number of DIMMs loading CH A*/ @@ -233,16 +233,16 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DATAload[2]; /* Number of ranks loading CH A DATA*/ /* Number of ranks loading CH B DATA*/ u8 DIMMAutoSpeed; /* Max valid Mfg. Speed of DIMMs - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz */ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz */ u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ @@ -252,16 +252,16 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/ u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/ u8 Speed; /* Bus Speed (to set Controller) - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz */ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz */ u8 CASL; /* CAS latency DCT setting - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u8 Trcd; /* DCT Trcd (busclocks) */ u8 Trp; /* DCT Trp (busclocks) */ u8 Trtp; /* DCT Trtp (busclocks) */ @@ -271,27 +271,27 @@ struct DCTStatStruc { /* A per Node structure*/ u8 Trrd; /* DCT Trrd (busclocks) */ u8 Twtr; /* DCT Twtr (busclocks) */ u8 Trfc[4]; /* DCT Logical DIMM0 Trfc - 0=75ns (for 256Mb devs) - 1=105ns (for 512Mb devs) - 2=127.5ns (for 1Gb devs) - 3=195ns (for 2Gb devs) - 4=327.5ns (for 4Gb devs) */ + 0 = 75ns (for 256Mb devs) + 1 = 105ns (for 512Mb devs) + 2 = 127.5ns (for 1Gb devs) + 3 = 195ns (for 2Gb devs) + 4 = 327.5ns (for 4Gb devs) */ /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */ - u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */ - u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */ + u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */ + u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */ u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */ u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */ u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */ u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800) */ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800) */ u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode) - 1=1T - 2=2T */ + 1 = 1T + 2 = 2T */ u8 TrwtTO; /* DCT TrwtTO (busclocks)*/ u8 Twrrd; /* DCT Twrrd (busclocks)*/ u8 Twrwr; /* DCT Twrwr (busclocks)*/ @@ -319,9 +319,9 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB DIMM 0 - 3 Receiver Enable Delay*/ u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/ u32 PtrPatternBufB; /*Ptr on stack to aligned DQS testing pattern*/ - u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/ + u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/ u8 ByteLane; /* Current Byte Lane (0..7)*/ - u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/ + u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/ u8 Pattern; /* Current pattern*/ u8 DQSDelay; /* Current DQS delay value*/ u32 TrainErrors; /* Current Training Errors*/ @@ -399,72 +399,72 @@ struct DCTStatStruc { /* A per Node structure*/ ===============================================================================*/ /* Platform Configuration */ #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0=NPT L1 - 1=NPT M2 - 2=NPT S1*/ + 0 = NPT L1 + 1 = NPT M2 + 2 = NPT S1*/ #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800)*/ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800)*/ #define NV_ECC_CAP 4 /* Bus ECC capable (1-bits) - 0=Platform not capable - 1=Platform is capable*/ + 0 = Platform not capable + 1 = Platform is capable*/ #define NV_4RANKType 5 /* Quad Rank DIMM slot type (2-bits) - 0=Normal - 1=R4 (4-Rank Registered DIMMs in AMD server configuration) - 2=S4 (Unbuffered SO-DIMMs)*/ + 0 = Normal + 1 = R4 (4-Rank Registered DIMMs in AMD server configuration) + 2 = S4 (Unbuffered SO-DIMMs)*/ #define NV_BYPMAX 6 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4=4 times bypass (normal for non-UMA systems) - 7=7 times bypass (normal for UMA systems)*/ + 4 = 4 times bypass (normal for non-UMA systems) + 7 = 7 times bypass (normal for UMA systems)*/ #define NV_RDWRQBYP 7 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2=8 times (normal for non-UMA systems) - 3=16 times (normal for UMA systems)*/ + 2 = 8 times (normal for non-UMA systems) + 3 = 16 times (normal for UMA systems)*/
/* Dram Timing */ #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0=Auto, no user limit - 1=Auto, user limit provided in NV_MemCkVal - 2=Manual, user value provided in NV_MemCkVal*/ + 0 = Auto, no user limit + 1 = Auto, user limit provided in NV_MemCkVal + 2 = Manual, user value provided in NV_MemCkVal*/ #define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0=200MHz - 1=266MHz - 2=333MHz - 3=400MHz*/ + 0 = 200MHz + 1 = 266MHz + 2 = 333MHz + 3 = 400MHz*/
/* Dram Configuration */ #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0=normal - 1=enable all memclocks*/ + 0 = normal + 1 = enable all memclocks*/ #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0=Exit current node init if any DIMM has SPD checksum error - 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ + 0 = Exit current node init if any DIMM has SPD checksum error + 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0=skip DQS training - 1=perform DQS training*/ + 0 = skip DQS training + 1 = perform DQS training*/ #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_BurstLen32 25 /* burstLength32 for 64-bit mode (1-bits) - 0=disable (normal) - 1=enable (4 beat burst when width is 64-bits)*/ + 0 = disable (normal) + 1 = enable (4 beat burst when width is 64-bits)*/
/* Dram Power */ #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0=per Channel control - 1=per Chip select control*/ + 0 = per Channel control + 1 = per Chip select control*/ #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/
/* Memory Map/Mgt.*/ #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) @@ -472,8 +472,8 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) NV_BottomUMA[7:0]=Addr[31:24]*/ #define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0=disable - 1=enable */ + 0 = disable + 1 = enable */
/* ECC */ #define NV_ECC 50 /* Dram ECC enable*/ @@ -484,14 +484,14 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/ #define NV_DCBKScrub 57 /* DCache ECC Background Scrubber CTL*/ #define NV_CS_SpareCTL 58 /* Chip Select Spare Control bit 0: - 0=disable Spare - 1=enable Spare */ + 0 = disable Spare + 1 = enable Spare */ /*Chip Select Spare Control bit 1-4: Reserved, must be zero*/ #define NV_Parity 60 /* Parity Enable*/ #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/
/* global function */ diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 16e67df..c9bc565 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -195,7 +195,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, * 1. Complete Hypertransport Bus Configuration * 2. SMBus Controller Initialized * 3. Checksummed or Valid NVRAM bits - * 4. MCG_CTL=-1, MC4_CTL_EN=0 for all CPUs + * 4. MCG_CTL=-1, MC4_CTL_EN = 0 for all CPUs * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to * entry * 6. All var MTRRs reset to zero @@ -434,7 +434,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
} } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { SetEccDQSRcvrEn_D(pDCTstat, Channel); }
@@ -452,7 +452,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, * + 0x100 to next dimm */ for (DIMM = 0; DIMM < 2; DIMM++) { - if (DIMM==0) { + if (DIMM == 0) { index = 0; /* CHA Write Data Timing Low */ } else { if (pDCTstat->Speed >= 4) { @@ -461,7 +461,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, break; } } - for (Dir=0;Dir<2;Dir++) {//RD/WR + for (Dir = 0;Dir < 2;Dir++) {//RD/WR p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait(dev, index_reg, index+1, val); @@ -474,7 +474,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } }
- for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { reg = 0x78 + Channel * 0x100; val = Get_NB32(dev, reg); val &= ~(0x3ff<<22); @@ -834,7 +834,7 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst u32 reg_off = dct * 0x100; val = 1<<DisDramInterface; Set_NB32(pDCTstat->dev_dct, reg_off+0x94, val); - /*To maximize power savings when DisDramInterface=1b, + /*To maximize power savings when DisDramInterface = 1b, all of the MemClkDis bits should also be set.*/ val = 0xFF000000; Set_NB32(pDCTstat->dev_dct, reg_off+0x88, val); @@ -1013,7 +1013,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, Trc = 0; Twr = 0; Twtr = 0; - for (i=0; i < 4; i++) + for (i = 0; i < 4; i++) Trfc[i] = 0;
for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) { @@ -1062,13 +1062,13 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, if (Trc < val) Trc = val;
- /* dev density=rank size/#devs per rank */ + /* dev density = rank size/#devs per rank */ byte = mctRead_SPD(smbaddr, SPD_BANKSZ);
val = ((byte >> 5) | (byte << 3)) & 0xFF; val <<= 2;
- byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density=2^(rows+columns+banks) */ + byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density = 2^(rows+columns+banks) */ if (byte == 4) { val >>= 4; } else if (byte == 8) { @@ -1260,7 +1260,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
/* Trfc0-Trfc3 */ - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) pDCTstat->Trfc[i] = Trfc[i];
mctAdjustAutoCycTmg_D(); @@ -1329,7 +1329,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, DramTimingHi |= val<<16;
val = 0; - for (i=4;i>0;i--) { + for (i = 4; i>0; i--) { val <<= 3; val |= Trfc[i-1]; } @@ -1426,7 +1426,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
CL1min = 0xFF; T1min = 0xFF; - for (k=K_MAX; k >= K_MIN; k--) { + for (k = K_MAX; k >= K_MIN; k--) { for (j = J_MIN; j <= J_MAX; j++) { if (Sys_Capability_D(pMCTstat, pDCTstat, j, k) ) { /* 1. check to see if DIMMi is populated. @@ -1795,7 +1795,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, /* 13 Rows is smallest dev size */ byte |= Rows - 13; /* CCCBRR internal encode */
- for (dword=0; dword < 12; dword++) { + for (dword = 0; dword < 12; dword++) { if (byte == Tab_BankAddr[dword]) break; } @@ -1810,7 +1810,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, or 2pow(rows+cols+banks-5)-1*/ csMask = 0;
- byte = Rows + Cols; /* cl=rows+cols*/ + byte = Rows + Cols; /* cl = rows+cols*/ if (Banks == 8) byte -= 2; /* 3 banks - 5 */ else @@ -1881,7 +1881,7 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat,
/* Check Symmetry of Channel A and Channel B DIMMs (must be matched for 128-bit mode).*/ - for (i=0; i < MAX_DIMMS_SUPPORTED; i += 2) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i += 2) { if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) { smbaddr = Get_DIMMAddress_D(pDCTstat, i); smbaddr1 = Get_DIMMAddress_D(pDCTstat, i+1); @@ -1952,7 +1952,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
_DSpareEn = 0;
- /* CS Sparing 1=enabled, 0=disabled */ + /* CS Sparing 1 = enabled, 0 = disabled */ if (mctGet_NVbits(NV_CS_SpareCTL) & 1) { if (MCT_DIMM_SPARE_NO_WARM) { /* Do no warm-reset DIMM spare */ @@ -1967,7 +1967,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, pDCTstat->ErrStatus |= 1 << SB_SpareDis; } } else { - if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1=enabled, 0=disabled */ + if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1 = enabled, 0 = disabled */ word = pDCTstat->CSPresent; val = bsf(word); word &= ~(1 << val); @@ -1981,13 +1981,13 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, }
nxtcsBase = 0; /* Next available cs base ADDR[39:8] */ - for (p=0; p < MAX_DIMMS_SUPPORTED; p++) { + for (p = 0; p < MAX_DIMMS_SUPPORTED; p++) { BiggestBank = 0; for (q = 0; q < MAX_CS_SUPPORTED; q++) { /* from DIMMS to CS */ if (pDCTstat->CSPresent & (1 << q)) { /* bank present? */ reg = 0x40 + (q << 2) + reg_off; /* Base[q] reg.*/ val = Get_NB32(dev, reg); - if (!(val & 3)) { /* (CSEnable|Spare==1)bank is enabled already? */ + if (!(val & 3)) { /* (CSEnable|Spare == 1)bank is enabled already? */ reg = 0x60 + ((q << 1) & 0xc) + reg_off; /*Mask[q] reg.*/ val = Get_NB32(dev, reg); val >>= 19; @@ -2003,7 +2003,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } /*if bank present */ } /* while q */ if (BiggestBank !=0) { - curcsBase = nxtcsBase; /* curcsBase=nxtcsBase*/ + curcsBase = nxtcsBase; /* curcsBase = nxtcsBase*/ /* DRAM CS Base b Address Register offset */ reg = 0x40 + (b << 2) + reg_off; if (_DSpareEn) { @@ -2121,12 +2121,12 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, /* Check DIMMs present, verify checksum, flag SDRAM type, * build population indicator bitmaps, and preload bus loading * of DIMMs into DCTStatStruc. - * MAAload=number of devices on the "A" bus. - * MABload=number of devices on the "B" bus. - * MAAdimms=number of DIMMs on the "A" bus slots. - * MABdimms=number of DIMMs on the "B" bus slots. - * DATAAload=number of ranks on the "A" bus slots. - * DATABload=number of ranks on the "B" bus slots. + * MAAload = number of devices on the "A" bus. + * MABload = number of devices on the "B" bus. + * MAAdimms = number of DIMMs on the "A" bus slots. + * MABdimms = number of DIMMs on the "B" bus slots. + * DATAAload = number of ranks on the "A" bus slots. + * DATABload = number of ranks on the "B" bus slots. */
u16 i, j, k; @@ -2159,7 +2159,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, print_tx("\t DIMMPresence: smbaddr=", smbaddr); if (smbaddr) { Checksum = 0; - for (Index=0; Index < 64; Index++){ + for (Index = 0; Index < 64; Index++){ int status; status = mctRead_SPD(smbaddr, Index); if (status < 0) @@ -2274,7 +2274,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, if (devwidth == 16) bytex = 4; else if (devwidth == 4) - bytex=16; + bytex = 16;
if (byte == 2) bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/ @@ -2595,7 +2595,7 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, i_start = dct; i_end = dct + 1; } - for (i=i_start; i<i_end; i++) { + for (i = i_start; i < i_end; i++) { index_reg = 0x98 + (i * 0x100); Set_NB32_index_wait(dev, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A Output Driver Compensation Control */ Set_NB32_index_wait(dev, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A Output Driver Compensation Control */ @@ -3022,7 +3022,7 @@ static u8 Check_DqsRcvEn_Diff(struct DCTStatStruc *pDCTstat, if (index == 0x12) ecc_reg = 1;
- for (i=0; i < 8; i+=2) { + for (i = 0; i < 8; i+=2) { if ( pDCTstat->DIMMValid & (1 << i)) { val = Get_NB32_index_wait(dev, index_reg, index); byte = val & 0xFF; @@ -3153,7 +3153,7 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat, if (index == 0x12) ecc_reg = 1;
- for (i=0; i < 8; i+=2) { + for (i = 0; i < 8; i+=2) { if ( pDCTstat->DIMMValid & (1 << i)) { val = Get_NB32_index_wait(dev, index_reg, index); val &= 0x00E000E0; @@ -3192,11 +3192,11 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
Smallest = 3; Largest = 0; - for (i=0; i < 2; i++) { + for (i = 0; i < 2; i++) { val = Get_NB32_index_wait(dev, index_reg, index); val &= 0x60606060; val >>= 5; - for (j=0; j < 4; j++) { + for (j = 0; j < 4; j++) { byte = val & 0xFF; if (byte < Smallest) Smallest = byte; @@ -3308,7 +3308,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
/* Copy dram map from F1x40/44,F1x48/4c, to F1x120/124(Node0),F1x120/124(Node1),...*/ - for (Node=0; Node < MAX_NODES_SUPPORTED; Node++) { + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { pDCTstat = pDCTstatA + Node; devx = pDCTstat->dev_map;
@@ -3476,7 +3476,7 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
val = Get_NB32_index_wait(dev, index_reg, 0x00); dword = 0; - for (i=0; i < 6; i++) { + for (i = 0; i < 6; i++) { switch (i) { case 0: case 4: @@ -3653,7 +3653,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
// FIXME: skip for Ax if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz - for (i=0; i < 2; i++) { + for (i = 0; i < 2; i++) { reg_off = 0x100 * i; Set_NB32(dev, 0x98 + reg_off, 0x0D000030); Set_NB32(dev, 0x9C + reg_off, 0x00000806); @@ -3990,9 +3990,9 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
/* ========================================================== * 6-bit Bank Addressing Table - * RR=rows-13 binary - * B=Banks-2 binary - * CCC=Columns-9 binary + * RR = rows-13 binary + * B = Banks-2 binary + * CCC = Columns-9 binary * ========================================================== * DCT CCCBRR Rows Banks Columns 64-bit CS Size * Encoding diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index b580457..4e1a909 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -30,16 +30,16 @@ #define PT_S1 2 #define PT_GR 3
-#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/ -#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T*/ -#define K_MIN 1 /* k loop constraint. 1=200 MHz*/ -#define K_MAX 5 /* k loop constraint. 5=533 MHz*/ -#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/ -#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/ - -#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/ +#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/ +#define J_MAX 5 /* j loop constraint. 5 = CL 7.0 T*/ +#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/ +#define K_MAX 5 /* k loop constraint. 5 = 533 MHz*/ +#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/ +#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/ + +#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/ /* memory initialization (ecc and check-bits).*/ - /* 1=40 ns/64 bytes.*/ + /* 1 = 40 ns/64 bytes.*/ #define FirstPass 1 /* First pass through RcvEn training*/ #define SecondPass 2 /* Second pass through Rcven training*/
@@ -289,7 +289,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller*/ uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ - uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */ + uint8_t Dual_Node_Package; /* 1 = Dual node package (G34) */ uint8_t stopDCT; /* Set if the DCT will be stopped */ u8 ErrCode; /* Current error condition of Node 0= no error @@ -306,7 +306,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* SPD address of..MB2_CS_L[0,1]*/ /* SPD address of..MA3_CS_L[0,1]*/ /* SPD address of..MB3_CS_L[0,1]*/ - u16 DIMMPresent; /*For each bit n 0..7, 1=DIMM n is present. + u16 DIMMPresent; /*For each bit n 0..7, 1 = DIMM n is present. DIMM# Select Signal 0 MA0_CS_L[0,1] 1 MB0_CS_L[0,1] @@ -316,15 +316,15 @@ struct DCTStatStruc { /* A per Node structure*/ 5 MB2_CS_L[0,1] 6 MA3_CS_L[0,1] 7 MB3_CS_L[0,1]*/ - u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/ - u16 DIMMMismatch; /* For each bit n 0..7, 1=DIMM n is mismatched, channel B is always considered the mismatch */ - u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/ - u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/ - u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/ - u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/ - u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/ - u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/ - u16 DIMM2Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/ + u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/ + u16 DIMMMismatch; /* For each bit n 0..7, 1 = DIMM n is mismatched, channel B is always considered the mismatch */ + u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/ + u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/ + u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/ + u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/ + u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/ + u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/ + u16 DIMM2Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/ u8 MAload[2]; /* Number of devices loading MAA bus*/ /* Number of devices loading MAB bus*/ u8 MAdimms[2]; /*Number of DIMMs loading CH A*/ @@ -332,17 +332,17 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DATAload[2]; /*Number of ranks loading CH A DATA*/ /* Number of ranks loading CH B DATA*/ u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz - 5=533MHz*/ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz + 5 = 533MHz*/ u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ @@ -352,16 +352,16 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/ u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/ u8 Speed; /* Bus Speed (to set Controller) - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz */ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz */ u8 CASL; /* CAS latency DCT setting - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u8 Trcd; /* DCT Trcd (busclocks) */ u8 Trp; /* DCT Trp (busclocks) */ u8 Trtp; /* DCT Trtp (busclocks) */ @@ -371,27 +371,27 @@ struct DCTStatStruc { /* A per Node structure*/ u8 Trrd; /* DCT Trrd (busclocks) */ u8 Twtr; /* DCT Twtr (busclocks) */ u8 Trfc[4]; /* DCT Logical DIMM0 Trfc - 0=75ns (for 256Mb devs) - 1=105ns (for 512Mb devs) - 2=127.5ns (for 1Gb devs) - 3=195ns (for 2Gb devs) - 4=327.5ns (for 4Gb devs) */ + 0 = 75ns (for 256Mb devs) + 1 = 105ns (for 512Mb devs) + 2 = 127.5ns (for 1Gb devs) + 3 = 195ns (for 2Gb devs) + 4 = 327.5ns (for 4Gb devs) */ /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */ - u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */ - u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */ + u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */ + u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */ u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */ u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */ u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */ u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800) */ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800) */ u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode) - 1=1T - 2=2T */ + 1 = 1T + 2 = 2T */ u8 TrwtTO; /* DCT TrwtTO (busclocks)*/ u8 Twrrd; /* DCT Twrrd (busclocks)*/ u8 Twrwr; /* DCT Twrwr (busclocks)*/ @@ -415,9 +415,9 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB Byte 0-7 Read DQS Delay */ u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/ u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/ - u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/ + u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/ u8 ByteLane; /* Current Byte Lane (0..7)*/ - u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/ + u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/ u8 Pattern; /* Current pattern*/ u8 DQSDelay; /* Current DQS delay value*/ u32 TrainErrors; /* Current Training Errors*/ @@ -483,15 +483,15 @@ struct DCTStatStruc { /* A per Node structure*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL; // NOTE: Not used - u8 NodeSpeed /* Bus Speed (to set Controller) - /* 1=200MHz */ - /* 2=266MHz */ - /* 3=333MHz */ + /* 1 = 200MHz */ + /* 2 = 266MHz */ + /* 3 = 333MHz */ // NOTE: Not used - u8 NodeCASL /* CAS latency DCT setting - /* 0=2.0 */ - /* 1=3.0 */ - /* 2=4.0 */ - /* 3=5.0 */ - /* 4=6.0 */ + /* 0 = 2.0 */ + /* 1 = 3.0 */ + /* 2 = 4.0 */ + /* 3 = 5.0 */ + /* 4 = 6.0 */ u8 TrwtWB; u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/ u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/ @@ -575,7 +575,7 @@ struct DCTStatStruc { /* A per Node structure*/ #define SB_SWNodeHole 7 /* Remapping of Node Base on this Node to create a gap.*/ #define SB_HWHole 8 /* Memory Hole created on this Node using HW remapping.*/ #define SB_Over400MHz 9 /* DCT freq >= 400MHz flag*/ -#define SB_DQSPos_Pass2 10 /* Using for TrainDQSPos DIMM0/1, when freq>=400MHz*/ +#define SB_DQSPos_Pass2 10 /* Using for TrainDQSPos DIMM0/1, when freq >= 400MHz*/ #define SB_DQSRcvLimit 11 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/ #define SB_ExtConfig 12 /* Indicator the default setting for extend PCI configuration support*/
@@ -587,73 +587,73 @@ struct DCTStatStruc { /* A per Node structure*/ ===============================================================================*/ /*Platform Configuration*/ #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0=NPT L1 - 1=NPT M2 - 2=NPT S1*/ + 0 = NPT L1 + 1 = NPT M2 + 2 = NPT S1*/ #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800)*/ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800)*/ #define NV_MIN_MEMCLK 4 /* Minimum platform demonstrated Memclock (10-bits) */ #define NV_ECC_CAP 5 /* Bus ECC capable (1-bits) - 0=Platform not capable - 1=Platform is capable*/ + 0 = Platform not capable + 1 = Platform is capable*/ #define NV_4RANKType 6 /* Quad Rank DIMM slot type (2-bits) - 0=Normal - 1=R4 (4-Rank Registered DIMMs in AMD server configuration) - 2=S4 (Unbuffered SO-DIMMs)*/ + 0 = Normal + 1 = R4 (4-Rank Registered DIMMs in AMD server configuration) + 2 = S4 (Unbuffered SO-DIMMs)*/ #define NV_BYPMAX 7 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4=4 times bypass (normal for non-UMA systems) - 7=7 times bypass (normal for UMA systems)*/ + 4 = 4 times bypass (normal for non-UMA systems) + 7 = 7 times bypass (normal for UMA systems)*/ #define NV_RDWRQBYP 8 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2=8 times (normal for non-UMA systems) - 3=16 times (normal for UMA systems)*/ + 2 = 8 times (normal for non-UMA systems) + 3 = 16 times (normal for UMA systems)*/
/*Dram Timing*/ #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0=Auto, no user limit - 1=Auto, user limit provided in NV_MemCkVal - 2=Manual, user value provided in NV_MemCkVal*/ + 0 = Auto, no user limit + 1 = Auto, user limit provided in NV_MemCkVal + 2 = Manual, user value provided in NV_MemCkVal*/ #define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0=200MHz - 1=266MHz - 2=333MHz - 3=400MHz*/ + 0 = 200MHz + 1 = 266MHz + 2 = 333MHz + 3 = 400MHz*/
/*Dram Configuration*/ #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0=normal - 1=enable all memclocks*/ + 0 = normal + 1 = enable all memclocks*/ #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0=Exit current node init if any DIMM has SPD checksum error - 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ + 0 = Exit current node init if any DIMM has SPD checksum error + 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0=skip DQS training - 1=perform DQS training*/ + 0 = skip DQS training + 1 = perform DQS training*/ #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits) - 0=disable (normal) - 1=enable (4 beat burst when width is 64-bits)*/ + 0 = disable (normal) + 1 = enable (4 beat burst when width is 64-bits)*/
/*Dram Power*/ #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0=per Channel control - 1=per Chip select control*/ + 0 = per Channel control + 1 = per Chip select control*/ #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/
/*Memory Map/Mgt.*/ #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) @@ -661,8 +661,8 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) NV_BottomUMA[7:0]=Addr[31:24]*/ #define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0=disable - 1=enable */ + 0 = disable + 1 = enable */
/*ECC*/ #define NV_ECC 50 /* Dram ECC enable*/ @@ -674,13 +674,13 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_L3BKScrub 57 /* L3 ECC Background Scrubber CTL*/ #define NV_DCBKScrub 58 /* DCache ECC Background Scrubber CTL*/ #define NV_CS_SpareCTL 59 /* Chip Select Spare Control bit 0: - 0=disable Spare - 1=enable Spare */ + 0 = disable Spare + 1 = enable Spare */ /* Chip Select Spare Control bit 1-4: Reserved, must be zero*/ #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_Unganged 62
#define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits) diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index fd39b38..4338072 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -61,7 +61,7 @@ static u32 bsr(u32 x) u8 i; u32 ret = 0;
- for (i=31; i>0; i--) { + for (i = 31; i>0; i--) { if (x & (1<<i)) { ret = i; break; @@ -78,7 +78,7 @@ static u32 bsf(u32 x) u8 i; u32 ret = 32;
- for (i=0; i<32; i++) { + for (i = 0; i < 32; i++) { if (x & (1<<i)) { ret = i; break; @@ -343,7 +343,7 @@ static u32 stream_to_int(u8 const *p)
val = 0;
- for (i=3; i>=0; i--) { + for (i = 3; i >= 0; i--) { val <<= 8; valx = *(p+i); val |= valx; diff --git a/src/northbridge/amd/amdmct/mct/mctchi_d.c b/src/northbridge/amd/amdmct/mct/mctchi_d.c index d5956b1..8d73a77 100644 --- a/src/northbridge/amd/amdmct/mct/mctchi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctchi_d.c @@ -37,7 +37,7 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, /* call back to wrapper not needed ManualChannelInterleave_D(); */ /* call back - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv);*/ /* override interleave */ // FIXME: Check for Cx - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ=5: Hash*: exclusive OR of address bits[20:16, 6]. */ + DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ = 5: Hash*: exclusive OR of address bits[20:16, 6]. */ beforeInterleaveChannels_D(pDCTstatA, &enabled);
if (DctSelIntLvAddr & 1) { diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 67ff823..558b1a9 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -226,7 +226,7 @@ static void SetEccDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, pDCTstat->Channel = channel; /* Channel A or B */ pDCTstat->Direction = direction; /* Read or write */ CalcEccDQSPos_D(pMCTstat, pDCTstat, pDCTstat->CH_EccDQSLike[channel], pDCTstat->CH_EccDQSScale[channel], ChipSel); - print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); + print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); pDCTstat->ByteLane = 8; StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel); @@ -362,7 +362,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); } @@ -411,11 +411,11 @@ static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); if (pDCTstat->Status & (1 << SB_128bitmode)) { pDCTstat->Pattern = 1; /* 18 cache lines, alternating qwords */ - for (i=0; i<16*18; i++) + for (i = 0; i < 16*18; i++) buf[i] = TestPatternJD1b_D[i]; } else { pDCTstat->Pattern = 0; /* 9 cache lines, sequential qwords */ - for (i=0; i<16*9; i++) + for (i = 0; i < 16*9; i++) buf[i] = TestPatternJD1a_D[i]; } pDCTstat->PtrPatternBufA = (u32)buf; @@ -458,10 +458,10 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, dqsDelay_end = 32; }
- /* Bitmapped status per delay setting, 0xff=All positions + /* Bitmapped status per delay setting, 0xff = All positions * passing (1= PASS). Set the entire array. */ - for (DQSDelay=0; DQSDelay<64; DQSDelay++) { + for (DQSDelay = 0; DQSDelay < 64; DQSDelay++) { MutualCSPassW[DQSDelay] = 0xFF; }
@@ -481,7 +481,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, }
print_debug_dqs("\t\t\t\tTrainDQSPos: 12 TestAddr ", TestAddr, 4); - SetUpperFSbase(TestAddr); /* fs:eax=far ptr to target */ + SetUpperFSbase(TestAddr); /* fs:eax = far ptr to target */
if (pDCTstat->Direction == DQS_READDIR) { print_debug_dqs("\t\t\t\tTrainDQSPos: 13 for read ", 0, 4); @@ -504,7 +504,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", pDCTstat->Pattern, 5); ReadDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); */ - tmp = CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* 0=fail, 1=pass */ + tmp = CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* 0 = fail, 1 = pass */
if (mct_checkFenceHoleAdjust_D(pMCTstat, pDCTstat, DQSDelay, ChipSel, &tmp)) { goto skipLocMiddle; @@ -775,8 +775,8 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatS }
bytelane = 0; /* bytelane counter */ - bitmap = 0xFF; /* bytelane test bitmap, 1=pass */ - for (i=0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ + bitmap = 0xFF; /* bytelane test bitmap, 1 = pass */ + for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ value = read32_fs(addr_lo); value_test = *test_buf;
@@ -1088,7 +1088,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat,
val &= ~0x0F;
- /* unganged mode DCT0+DCT1, sys addr of DCT1=node + /* unganged mode DCT0+DCT1, sys addr of DCT1 = node * base+DctSelBaseAddr+local ca base*/ if ((Channel) && (pDCTstat->GangedMode == 0) && ( pDCTstat->DIMMValidDCT[0] > 0)) { reg = 0x110; @@ -1104,7 +1104,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, val += dword; } } else { - /* sys addr=node base+local cs base */ + /* sys addr = node base+local cs base */ val += pDCTstat->DCTSysBase;
/* New stuff */ diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 5c1dc3a..fa2cf4d 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -40,7 +40,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); * * Conditions for setting background scrubber. * 1. node is present - * 2. node has dram functioning (WE=RE=1) + * 2. node has dram functioning (WE = RE = 1) * 3. all eccdimms (or bit 17 of offset 90,fn 2) * 4. no chip-select gap exists * @@ -300,7 +300,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) } else { ch_end = 2; } - for (i=0; i<ch_end; i++) { + for (i = 0; i < ch_end; i++) { if (pDCTstat->DIMMValidDCT[i] > 0){ reg = 0x90 + i * 0x100; /* Dram Config Low */ val = Get_NB32(dev, reg); diff --git a/src/northbridge/amd/amdmct/mct/mctgr.c b/src/northbridge/amd/amdmct/mct/mctgr.c index a13d4e2..5ac29fe 100644 --- a/src/northbridge/amd/amdmct/mct/mctgr.c +++ b/src/northbridge/amd/amdmct/mct/mctgr.c @@ -34,9 +34,9 @@ u32 mct_AdjustMemClkDis_GR(struct DCTStatStruc *pDCTstat, u32 dct, if (mctGet_NVbits(NV_AllMemClks)==0) { /*Special Jedec SPD diagnostic bit - "enable all clocks"*/ if (!(pDCTstat->Status & (1<<SB_DiagClks))) { - for (i=0; i<MAX_DIMMS_SUPPORTED; i++) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { val = Tab_GRCLKDis[i]; - if (val<8) { + if (val < 8) { if (!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) { /* disable memclk */ NewDramTimingLo |= (1<<(i+1)); diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c index 5e91947..57cce29 100644 --- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c @@ -35,11 +35,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
/* Set temporary top of memory from Node structure data. * Adjust temp top of memory down to accommodate 32-bit IO space. - * Bottom40bIO=top of memory, right justified 8 bits + * Bottom40bIO = top of memory, right justified 8 bits * (defines dram versus IO space type) - * Bottom32bIO=sub 4GB top of memory, right justified 8 bits + * Bottom32bIO = sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) - * Cache32bTOP=sub 4GB top of WB cacheable memory, + * Cache32bTOP = sub 4GB top of WB cacheable memory, * right justified 8 bits */
@@ -83,8 +83,8 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, */ addr = 0x204; /* MTRR phys base 2*/ /* use TOP_MEM as limit*/ - /* Limit=TOP_MEM|TOM2*/ - /* Base=0*/ + /* Limit = TOP_MEM|TOM2*/ + /* Base = 0*/ print_tx("\t CPUMemTyping: Cache32bTOP:", Cache32bTOP); SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); /* Base */ @@ -115,10 +115,10 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, addr = 0xC0010010; /* SYS_CFG */ _RDMSR(addr, &lo, &hi); if (Bottom40bIO) { - lo |= (1<<21); /* MtrrTom2En=1 */ + lo |= (1<<21); /* MtrrTom2En = 1 */ lo |= (1<<22); /* Tom2ForceMemTypeWB */ } else { - lo &= ~(1<<21); /* MtrrTom2En=0 */ + lo &= ~(1<<21); /* MtrrTom2En = 0 */ lo &= ~(1<<22); /* Tom2ForceMemTypeWB */ } _WRMSR(addr, lo, hi); @@ -151,7 +151,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) * next set bit in a forward or backward sequence of bits (as a function * of the Limit). We start with the ascending path, to ensure that * regions are naturally aligned, then we switch to the descending path - * to maximize MTRR usage efficiency. Base=0 is a special case where we + * to maximize MTRR usage efficiency. Base = 0 is a special case where we * start with the descending path. Correct Mask for region is * 2comp(Size-1)-1, which is 2comp(Limit-Base-1)-1 */ @@ -177,14 +177,14 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) curSize = valx; valx += curBase; } - curLimit = valx; /*eax=curBase, edx=curLimit*/ + curLimit = valx; /*eax = curBase, edx = curLimit*/ valx = val>>24; val <<= 8;
/* now program the MTRR */ val |= MtrrType; /* set cache type (UC or WB)*/ _WRMSR(addr, val, valx); /* prog. MTRR with current region Base*/ - val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask=2comp(Size-1)-1*/ + val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask = 2comp(Size-1)-1*/ valx = (val >> 24) | (0xff00); /* GH have 48 bits addr */ val <<= 8; val |= ( 1 << 11); /* set MTRR valid*/ @@ -217,9 +217,9 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat /*====================================================================== * Adjust temp top of memory down to accommodate UMA memory start *======================================================================*/ - /* Bottom32bIO=sub 4GB top of memory, right justified 8 bits + /* Bottom32bIO = sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) - * Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 8 bits */ + * Cache32bTOP = sub 4GB top of WB cacheable memory, right justified 8 bits */
Bottom32bIO = pMCTstat->Sub4GCacheTop >> 8;
diff --git a/src/northbridge/amd/amdmct/mct/mctndi_d.c b/src/northbridge/amd/amdmct/mct/mctndi_d.c index 32c3199..7b7699a 100644 --- a/src/northbridge/amd/amdmct/mct/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctndi_d.c @@ -144,7 +144,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, if (DoIntlv) { MCTMemClr_D(pMCTstat,pDCTstatA); /* Program Interleaving enabled on Node 0 map only.*/ - MemSize0 <<= bsf(Nodes); /* MemSize=MemSize*2 (or 4, or 8) */ + MemSize0 <<= bsf(Nodes); /* MemSize = MemSize*2 (or 4, or 8) */ Dct0MemSize <<= bsf(Nodes); MemSize0 += HWHoleSz; Base = ((Nodes - 1) << 8) | 3; diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 95afebf..c17014b 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -69,7 +69,7 @@ void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct) val |= 1<<BurstLength32; Set_NB32(dev, reg, val);
- reg = 0x88 + reg_off; /* cx=Dram Timing Lo */ + reg = 0x88 + reg_off; /* cx = Dram Timing Lo */ val = Get_NB32(dev, reg); val |= 0x000F0000; /* Trc = 0Fh */ Set_NB32(dev, reg, val); @@ -149,14 +149,14 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, dev = pDCTstat->dev_dct; index = 0;
- for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { index_reg = 0x98 + 0x100 * Channel; val = Get_NB32_index_wait(dev, index_reg, 0x0d004007); val |= 0x3ff; Set_NB32_index_wait(dev, index_reg, 0x0d0f4f07, val); }
- for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { if (pDCTstat->GangedMode && Channel) break; reg_off = 0x100 * Channel; @@ -167,7 +167,7 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, Set_NB32(dev, reg, val); }
- for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { reg_off = 0x100 * Channel; val = 0; index_reg = 0x98 + reg_off; @@ -265,7 +265,7 @@ u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct) print_tx("NB COF:", valy >> NbDid);
val = valy/valx; - if ((val==3) && (valy%valx)) /* 3 < NClk/MemClk < 4 */ + if ((val == 3) && (valy%valx)) /* 3 < NClk/MemClk < 4 */ ret = 1;
return ret; @@ -296,7 +296,7 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) } dev = pDCTstat->dev_dct; index = 0x0D00E001; - for (ch=ch_start; ch<ch_end; ch++) { + for (ch = ch_start; ch < ch_end; ch++) { index_reg = 0x98 + 0x100 * ch; val = Get_NB32_index(dev, index_reg, 0x0D00E001); val &= ~(0xf0); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 510cf0d..aa3f6d66 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -86,7 +86,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, p_A = (u32 *)SetupDqsPattern_1PassB(pass); p_B = (u32 *)SetupDqsPattern_1PassA(pass);
- for (i=0;i<16;i++) { + for (i = 0; i < 16; i++) { buf_a[i] = p_A[i]; buf_b[i] = p_B[i]; } @@ -261,7 +261,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, if (Pass == FirstPass) { pDCTstat->DqsRcvEn_Pass = 0; } else { - pDCTstat->DqsRcvEn_Pass=0xFF; + pDCTstat->DqsRcvEn_Pass = 0xFF; } pDCTstat->DqsRcvEn_Saved = 0;
@@ -456,7 +456,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, { u8 Channel; printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); } } @@ -472,10 +472,10 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); for (Channel = 0; Channel < 2; Channel++) { printk(BIOS_DEBUG, "Channel: %02x\n", Channel); - for (Receiver = 0; Receiver<8; Receiver+=2) { + for (Receiver = 0; Receiver < 8; Receiver+=2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); } @@ -526,7 +526,7 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat) ch_end = 2; }
- for (ch=0; ch<ch_end; ch++) { + for (ch = 0; ch < ch_end; ch++) { reg = 0x78 + 0x100 * ch; val = Get_NB32(dev, reg); val &= ~(1 << DqsRcvEnTrain); @@ -562,14 +562,14 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, /* DimmOffset not needed for CH_D_B_RCVRDLY array */
- for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; }
- /* if flag=0, set DqsRcvEn value to reg. */ + /* if flag = 0, set DqsRcvEn value to reg. */ /* get the register index from table */ index = Table_DQSRcvEn_Offset[i >> 1]; index += Addl_Index; /* DIMMx DqsRcvEn byte0 */ @@ -723,7 +723,7 @@ static u8 mct_SavePassRcvEnDly_D(struct DCTStatStruc *pDCTstat, mask_Saved &= mask_Pass; p = pDCTstat->CH_D_B_RCVRDLY[Channel][receiver>>1]; } - for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { /* cmp per byte lane */ if (mask_Pass & (1 << i)) { if (!(mask_Saved & (1 << i))) { @@ -757,7 +757,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat,
if (Pass == FirstPass) { - if (pattern==1) { + if (pattern == 1) { test_buf = (u8 *)TestPattern1_D; } else { test_buf = (u8 *)TestPattern0_D; @@ -775,7 +775,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, }
print_debug_dqs_pair("\t\t\t\t\t\t test_buf = ", (u32)test_buf, " | addr_lo = ", addr, 4); - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { value = read32_fs(addr); print_debug_dqs_pair("\t\t\t\t\t\t\t\t ", test_buf[i], " | ", value, 4);
@@ -790,7 +790,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat,
if (Pass == FirstPass) { /* if first pass, at least one byte lane pass - * ,then DQS_PASS=1 and will set to related reg. + * ,then DQS_PASS = 1 and will set to related reg. */ if (pDCTstat->DqsRcvEn_Pass != 0) { result = DQS_PASS; @@ -800,7 +800,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat,
} else { /* if second pass, at least one byte lane fail - * ,then DQS_FAIL=1 and will set to related reg. + * ,then DQS_FAIL = 1 and will set to related reg. */ if (pDCTstat->DqsRcvEn_Pass != 0xFF) { result = DQS_FAIL; @@ -843,7 +843,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, * Read Position is 1/2 Memclock Delay */ u8 i; - for (i=0;i<2; i++){ + for (i = 0; i < 2; i++){ InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -867,8 +867,8 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
// FIXME: add Cx support dword = 0x00000000; - for (i=1; i<=3; i++) { - for (j=0; j<dn; j++) + for (i = 1; i <= 3; i++) { + for (j = 0; j < dn; j++) /* DIMM0 Write Data Timing Low */ /* DIMM0 Write ECC Timing */ Set_NB32_index_wait(dev, index_reg, i + 0x100 * j, dword); @@ -876,14 +876,14 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
/* errata #180 */ dword = 0x2f2f2f2f; - for (i=5; i<=6; i++) { - for (j=0; j<dn; j++) + for (i = 5; i <= 6; i++) { + for (j = 0; j < dn; j++) /* DIMM0 Read DQS Timing Control Low */ Set_NB32_index_wait(dev, index_reg, i + 0x100 * j, dword); }
dword = 0x0000002f; - for (j=0; j<dn; j++) + for (j = 0; j < dn; j++) /* DIMM0 Read DQS ECC Timing Control */ Set_NB32_index_wait(dev, index_reg, 7 + 0x100 * j, dword); } @@ -969,7 +969,7 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, if (!pDCTstat->NodePresent) break; if (pDCTstat->DCTSysLimit) { - for (i=0; i<2; i++) + for (i = 0; i < 2; i++) CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i); } } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index e059e1e..c1b1133 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -50,7 +50,7 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, MaxValue = 0; p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1];
- for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ val = p[i]; /* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/ diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index bd3c503..9522264 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -62,7 +62,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; // print_tx("mct_Get_Start_RcvrEnDly_Pass: Channel:", Channel); // print_tx("mct_Get_Start_RcvrEnDly_Pass: Receiver:", Receiver); - for ( i=0;i<bn; i++) { + for ( i = 0; i < bn; i++) { val = p[i]; // print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i); // print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val); @@ -100,7 +100,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, //FIXME: which byte? p_1 = pDCTstat->B_RCVRDLY_1; // p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; - for (i=0; i<bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ if (val != (RcvrEnDlyLimit - 1)) { @@ -120,7 +120,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } } else { - for (i=0; i < bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ //val += Pass1MemClkDly; diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 0eb3c61..d007755 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -195,7 +195,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, { u8 Channel; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); } } @@ -213,7 +213,7 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat,
if (pDCTstat->GangedMode) { Channel = 0; // for safe - for (i=0; i<2; i++) + for (i = 0; i < 2; i++) pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal; } else { pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal; @@ -247,7 +247,7 @@ static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr) addr_lo = addr<<8;
_EXECFENCE; - for (i=0; i<(16*3); i++) { + for (i = 0; i<(16*3); i++) { val = read32_fs(addr_lo); val_test = test_buf[i];
@@ -292,8 +292,8 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, *valid = 0;
for (ch = ch_start; ch < ch_end; ch++) { - for (d=0; d<4; d++) { - for (Byte = 0; Byte<bn; Byte++) { + for (d = 0; d < 4; d++) { + for (Byte = 0; Byte < bn; Byte++) { u8 tmp; tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; if (tmp>Max) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 08d8d43..6730d66 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2625,7 +2625,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, * 1. BSP in Big Real Mode * 2. Stack at SS:SP, located somewhere between A000:0000 and F000:FFFF * 3. Checksummed or Valid NVRAM bits - * 4. MCG_CTL=-1, MC4_CTL_EN=0 for all CPUs + * 4. MCG_CTL=-1, MC4_CTL_EN = 0 for all CPUs * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry * 6. All var MTRRs reset to zero * 7. State of NB_CFG.DisDatMsk set properly on all CPUs @@ -3819,7 +3819,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { SetEccDQSRcvrEn_D(pDCTstat, Channel); }
@@ -3859,7 +3859,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } }
- for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { reg = 0x78; val = Get_NB32_DCT(dev, Channel, reg); val &= ~(0x3ff<<22); @@ -4223,7 +4223,7 @@ static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *p dword &= ~(1 << ParEn); Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x90, dword);
- /* To maximize power savings when DisDramInterface=1b, + /* To maximize power savings when DisDramInterface = 1b, * all of the MemClkDis bits should also be set. */ Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x88, 0xff000000); @@ -4369,16 +4369,16 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, Trc = 0; Twr = 0; Twtr = 0; - for (i=0; i < 2; i++) + for (i = 0; i < 2; i++) Etr[i] = 0; - for (i=0; i < 4; i++) + for (i = 0; i < 4; i++) Trfc[i] = 0; Tfaw = 0;
for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) { LDIMM = i >> 1; if (pDCTstat->DIMMValid & (1 << i)) { - val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; /* MTB=Dividend/Divisor */ + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; /* MTB = Dividend/Divisor */ MTB16x = ((pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDividend] & 0xff) << 4); MTB16x /= val; /* transfer to MTB*16 */
@@ -4574,7 +4574,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, pDCTstat->Twtr = val;
/* Trfc0-Trfc3 */ - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) pDCTstat->Trfc[i] = Trfc[i];
/* Tfaw */ @@ -4647,7 +4647,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, 0x204, dword); /* DRAM Timing 1 */
/* Trfc0-Trfc3 */ - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) if (pDCTstat->Trfc[i] == 0x0) pDCTstat->Trfc[i] = 0x1; dword = Get_NB32_DCT(dev, dct, 0x208); /* DRAM Timing 2 */ @@ -4714,7 +4714,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, DramTimingHi |= val<<16;
val = 0; - for (i=4;i>0;i--) { + for (i = 4; i>0; i--) { val <<= 3; val |= Trfc[i-1]; } @@ -5330,11 +5330,11 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
if (pDCTstat->DIMMValid & (1<<byte)) { byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Addressing]; - Rows = (byte >> 3) & 0x7; /* Rows:0b=12-bit,... */ - Cols = byte & 0x7; /* Cols:0b=9-bit,... */ + Rows = (byte >> 3) & 0x7; /* Rows:0b = 12-bit,... */ + Cols = byte & 0x7; /* Cols:0b = 9-bit,... */
byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Density]; - Banks = (byte >> 4) & 7; /* Banks:0b=3-bit,... */ + Banks = (byte >> 4) & 7; /* Banks:0b = 3-bit,... */
byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Organization]; Ranks = ((byte >> 3) & 7) + 1; @@ -5351,7 +5351,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
byte |= Rows << 3; /* RRRBCC internal encode */
- for (dword=0; dword < 13; dword++) { + for (dword = 0; dword < 13; dword++) { if (byte == Tab_BankAddr[dword]) break; } @@ -5367,7 +5367,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, or 2pow(rows+cols+banks-5)-1*/ csMask = 0;
- byte = Rows + Cols; /* cl=rows+cols*/ + byte = Rows + Cols; /* cl = rows+cols*/ byte += 21; /* row:12+col:9 */ byte -= 2; /* 3 banks - 5 */
@@ -5435,7 +5435,7 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat,
/* Check Symmetry of Channel A and Channel B DIMMs (must be matched for 128-bit mode).*/ - for (i=0; i < MAX_DIMMS_SUPPORTED; i += 2) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i += 2) { if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) { byte = pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x7; byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Addressing] & 0x7; @@ -5498,7 +5498,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
_DSpareEn = 0;
- /* CS Sparing 1=enabled, 0=disabled */ + /* CS Sparing 1 = enabled, 0 = disabled */ if (mctGet_NVbits(NV_CS_SpareCTL) & 1) { if (MCT_DIMM_SPARE_NO_WARM) { /* Do no warm-reset DIMM spare */ @@ -5513,7 +5513,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, pDCTstat->ErrStatus |= 1 << SB_SpareDis; } } else { - if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1=enabled, 0=disabled */ + if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1 = enabled, 0 = disabled */ word = pDCTstat->CSPresent; val = bsf(word); word &= ~(1 << val); @@ -5527,13 +5527,13 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, }
nxtcsBase = 0; /* Next available cs base ADDR[39:8] */ - for (p=0; p < MAX_DIMMS_SUPPORTED; p++) { + for (p = 0; p < MAX_DIMMS_SUPPORTED; p++) { BiggestBank = 0; for (q = 0; q < MAX_CS_SUPPORTED; q++) { /* from DIMMS to CS */ if (pDCTstat->CSPresent & (1 << q)) { /* bank present? */ reg = 0x40 + (q << 2); /* Base[q] reg.*/ val = Get_NB32_DCT(dev, dct, reg); - if (!(val & 3)) { /* (CSEnable|Spare==1)bank is enabled already? */ + if (!(val & 3)) { /* (CSEnable|Spare == 1)bank is enabled already? */ reg = 0x60 + (q << 1); /*Mask[q] reg.*/ val = Get_NB32_DCT(dev, dct, reg); val >>= 19; @@ -5549,7 +5549,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } /*if bank present */ } /* while q */ if (BiggestBank !=0) { - curcsBase = nxtcsBase; /* curcsBase=nxtcsBase*/ + curcsBase = nxtcsBase; /* curcsBase = nxtcsBase*/ /* DRAM CS Base b Address Register offset */ reg = 0x40 + (b << 2); if (_DSpareEn) { @@ -5611,12 +5611,12 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, /* Check DIMMs present, verify checksum, flag SDRAM type, * build population indicator bitmaps, and preload bus loading * of DIMMs into DCTStatStruc. - * MAAload=number of devices on the "A" bus. - * MABload=number of devices on the "B" bus. - * MAAdimms=number of DIMMs on the "A" bus slots. - * MABdimms=number of DIMMs on the "B" bus slots. - * DATAAload=number of ranks on the "A" bus slots. - * DATABload=number of ranks on the "B" bus slots. + * MAAload = number of devices on the "A" bus. + * MABload = number of devices on the "B" bus. + * MAAdimms = number of DIMMs on the "A" bus slots. + * MABdimms = number of DIMMs on the "B" bus slots. + * DATAAload = number of ranks on the "A" bus slots. + * DATABload = number of ranks on the "B" bus slots. */ u16 i, j, k; u8 smbaddr; @@ -5767,7 +5767,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, else if (devwidth == 2) bytex = 4;
- byte++; /* al+1=rank# */ + byte++; /* al+1 = rank# */ if (byte == 2) bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/
@@ -5961,7 +5961,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, val &= ~(1 << ParEn); Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x90, val);
- /* To maximize power savings when DisDramInterface=1b, + /* To maximize power savings when DisDramInterface = 1b, * all of the MemClkDis bits should also be set. */ Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x88, 0xff000000); @@ -6119,7 +6119,7 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, i_start = dct; i_end = dct + 1; } - for (i=i_start; i<i_end; i++) { + for (i = i_start; i < i_end; i++) { index_reg = 0x98; Set_NB32_index_wait_DCT(dev, i, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A/B Output Driver Compensation Control */ Set_NB32_index_wait_DCT(dev, i, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A/B Output Driver Compensation Control */ @@ -6568,7 +6568,7 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat, if (index == 0x12) ecc_reg = 1;
- for (i=0; i < 8; i+=2) { + for (i = 0; i < 8; i+=2) { if ( pDCTstat->DIMMValid & (1 << i)) { val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); val &= 0x00E000E0; @@ -6607,11 +6607,11 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
Smallest = 3; Largest = 0; - for (i=0; i < 2; i++) { + for (i = 0; i < 2; i++) { val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); val &= 0x60606060; val >>= 5; - for (j=0; j < 4; j++) { + for (j = 0; j < 4; j++) { byte = val & 0xFF; if (byte < Smallest) Smallest = byte; @@ -6774,7 +6774,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, /* ClrClToNB_D postponed until we're done executing from ROM */ mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat);
- /* set F3x8C[DisFastTprWr] on all DR, if L3Size=0 */ + /* set F3x8C[DisFastTprWr] on all DR, if L3Size = 0 */ if (pDCTstat->LogicalCPUID & AMD_DR_ALL) { if (!(cpuid_edx(0x80000006) & 0xFFFC0000)) { val = Get_NB32(pDCTstat->dev_nbmisc, 0x8C); @@ -6948,7 +6948,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
/* Copy dram map from F1x40/44,F1x48/4c, to F1x120/124(Node0),F1x120/124(Node1),...*/ - for (Node=0; Node < MAX_NODES_SUPPORTED; Node++) { + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { pDCTstat = pDCTstatA + Node; devx = pDCTstat->dev_map;
@@ -7328,7 +7328,7 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, } else { dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00); dword = 0; - for (i=0; i < 6; i++) { + for (i = 0; i < 6; i++) { switch (i) { case 0: case 4: @@ -7668,7 +7668,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, dword = 0x00000800; else dword = 0x00000000; - for (i=0; i < 2; i++) { + for (i = 0; i < 2; i++) { Set_NB32_DCT(dev, i, 0x98, 0x0D000030); Set_NB32_DCT(dev, i, 0x9C, dword); Set_NB32_DCT(dev, i, 0x98, 0x4D040F30); @@ -7958,11 +7958,11 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, DramMRS |= mct_DramTermDyn_RDimm(pMCTstat, pDCTstat, byte); }
- /* Qoff=0, output buffers enabled */ + /* Qoff = 0, output buffers enabled */ /* Tcwl */ DramMRS |= (pDCTstat->Speed - 4) << 20; - /* ASR=1, auto self refresh */ - /* SRT=0 */ + /* ASR = 1, auto self refresh */ + /* SRT = 0 */ DramMRS |= 1 << 18; }
@@ -8275,9 +8275,9 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
/* ========================================================== * 6-bit Bank Addressing Table - * RR=rows-13 binary - * B=Banks-2 binary - * CCC=Columns-9 binary + * RR = rows-13 binary + * B = Banks-2 binary + * CCC = Columns-9 binary * ========================================================== * DCT CCCBRR Rows Banks Columns 64-bit CS Size * Encoding @@ -8311,7 +8311,7 @@ uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm) for (Index = 0; Index < byte_use; Index ++) { byte = pDCTstat->spd_data.spd_bytes[dimm][Index]; CRC ^= byte << 8; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { if (CRC & 0x8000) { CRC <<= 1; CRC ^= 0x1021; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index e1d9da5..c42e452 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -33,16 +33,16 @@ #define PT_C3 5 #define PT_FM2 6
-#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/ -#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T*/ -#define K_MIN 1 /* k loop constraint. 1=200 MHz*/ -#define K_MAX 5 /* k loop constraint. 5=533 MHz*/ -#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/ -#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/ - -#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/ +#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/ +#define J_MAX 5 /* j loop constraint. 5 = CL 7.0 T*/ +#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/ +#define K_MAX 5 /* k loop constraint. 5 = 533 MHz*/ +#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/ +#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/ + +#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/ /* memory initialization (ecc and check-bits).*/ - /* 1=40 ns/64 bytes.*/ + /* 1 = 40 ns/64 bytes.*/ #define FirstPass 1 /* First pass through RcvEn training*/ #define SecondPass 2 /* Second pass through Rcven training*/
@@ -336,7 +336,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller */ uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ - uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */ + uint8_t Dual_Node_Package; /* 1 = Dual node package (G34) */ uint8_t stopDCT[2]; /* Set if the DCT will be stopped */ u8 ErrCode; /* Current error condition of Node 0= no error @@ -353,7 +353,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* SPD address of..MB2_CS_L[0,1]*/ /* SPD address of..MA3_CS_L[0,1]*/ /* SPD address of..MB3_CS_L[0,1]*/ - u16 DIMMPresent; /*For each bit n 0..7, 1=DIMM n is present. + u16 DIMMPresent; /*For each bit n 0..7, 1 = DIMM n is present. DIMM# Select Signal 0 MA0_CS_L[0,1] 1 MB0_CS_L[0,1] @@ -363,15 +363,15 @@ struct DCTStatStruc { /* A per Node structure*/ 5 MB2_CS_L[0,1] 6 MA3_CS_L[0,1] 7 MB3_CS_L[0,1]*/ - u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/ - u16 DIMMMismatch; /* For each bit n 0..7, 1=DIMM n is mismatched, channel B is always considered the mismatch */ - u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/ - u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/ - u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/ - u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/ - u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/ - u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/ - u16 DIMM2Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/ + u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/ + u16 DIMMMismatch; /* For each bit n 0..7, 1 = DIMM n is mismatched, channel B is always considered the mismatch */ + u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/ + u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/ + u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/ + u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/ + u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/ + u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/ + u16 DIMM2Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/ u8 MAload[2]; /* Number of devices loading MAA bus*/ /* Number of devices loading MAB bus*/ u8 MAdimms[2]; /*Number of DIMMs loading CH A*/ @@ -379,17 +379,17 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DATAload[2]; /*Number of ranks loading CH A DATA*/ /* Number of ranks loading CH B DATA*/ u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz - 5=533MHz*/ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz + 5 = 533MHz*/ u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ @@ -399,16 +399,16 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/ u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/ u8 Speed; /* Bus Speed (to set Controller) - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz */ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz */ u8 CASL; /* CAS latency DCT setting - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u8 Trcd; /* DCT Trcd (busclocks) */ u8 Trp; /* DCT Trp (busclocks) */ u8 Trtp; /* DCT Trtp (busclocks) */ @@ -418,27 +418,27 @@ struct DCTStatStruc { /* A per Node structure*/ u8 Trrd; /* DCT Trrd (busclocks) */ u8 Twtr; /* DCT Twtr (busclocks) */ u8 Trfc[4]; /* DCT Logical DIMM0 Trfc - 0=75ns (for 256Mb devs) - 1=105ns (for 512Mb devs) - 2=127.5ns (for 1Gb devs) - 3=195ns (for 2Gb devs) - 4=327.5ns (for 4Gb devs) */ + 0 = 75ns (for 256Mb devs) + 1 = 105ns (for 512Mb devs) + 2 = 127.5ns (for 1Gb devs) + 3 = 195ns (for 2Gb devs) + 4 = 327.5ns (for 4Gb devs) */ /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */ - u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */ - u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */ + u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */ + u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */ u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */ u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */ u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */ u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800) */ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800) */ u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode) - 1=1T - 2=2T */ + 1 = 1T + 2 = 2T */ u8 TrwtTO; /* DCT TrwtTO (busclocks)*/ u8 Twrrd; /* DCT Twrrd (busclocks)*/ u8 Twrwr; /* DCT Twrwr (busclocks)*/ @@ -462,9 +462,9 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB Byte 0-7 Read DQS Delay */ u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/ u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/ - u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/ + u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/ u8 ByteLane; /* Current Byte Lane (0..7)*/ - u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/ + u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/ u8 Pattern; /* Current pattern*/ u8 DQSDelay; /* Current DQS delay value*/ u32 TrainErrors; /* Current Training Errors*/ @@ -545,15 +545,15 @@ struct DCTStatStruc { /* A per Node structure*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL; /* NOTE: Not used - u8 NodeSpeed */ /* Bus Speed (to set Controller) */ - /* 1=200MHz */ - /* 2=266MHz */ - /* 3=333MHz */ + /* 1 = 200MHz */ + /* 2 = 266MHz */ + /* 3 = 333MHz */ /* NOTE: Not used - u8 NodeCASL */ /* CAS latency DCT setting */ - /* 0=2.0 */ - /* 1=3.0 */ - /* 2=4.0 */ - /* 3=5.0 */ - /* 4=6.0 */ + /* 0 = 2.0 */ + /* 1 = 3.0 */ + /* 2 = 4.0 */ + /* 3 = 5.0 */ + /* 4 = 6.0 */ u8 TrwtWB; u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/ u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/ @@ -852,7 +852,7 @@ struct amd_s3_persistent_data { #define SB_SWNodeHole 8 /* Remapping of Node Base on this Node to create a gap.*/ #define SB_HWHole 9 /* Memory Hole created on this Node using HW remapping.*/ #define SB_Over400MHz 10 /* DCT freq >= 400MHz flag*/ -#define SB_DQSPos_Pass2 11 /* Using for TrainDQSPos DIMM0/1, when freq>=400MHz*/ +#define SB_DQSPos_Pass2 11 /* Using for TrainDQSPos DIMM0/1, when freq >= 400MHz*/ #define SB_DQSRcvLimit 12 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/ #define SB_ExtConfig 13 /* Indicator the default setting for extend PCI configuration support*/
@@ -862,73 +862,73 @@ struct amd_s3_persistent_data { ===============================================================================*/ /*Platform Configuration*/ #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0=NPT L1 - 1=NPT M2 - 2=NPT S1*/ + 0 = NPT L1 + 1 = NPT M2 + 2 = NPT S1*/ #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800)*/ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800)*/ #define NV_MIN_MEMCLK 4 /* Minimum platform demonstrated Memclock (10-bits) */ #define NV_ECC_CAP 5 /* Bus ECC capable (1-bits) - 0=Platform not capable - 1=Platform is capable*/ + 0 = Platform not capable + 1 = Platform is capable*/ #define NV_4RANKType 6 /* Quad Rank DIMM slot type (2-bits) - 0=Normal - 1=R4 (4-Rank Registered DIMMs in AMD server configuration) - 2=S4 (Unbuffered SO-DIMMs)*/ + 0 = Normal + 1 = R4 (4-Rank Registered DIMMs in AMD server configuration) + 2 = S4 (Unbuffered SO-DIMMs)*/ #define NV_BYPMAX 7 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4=4 times bypass (normal for non-UMA systems) - 7=7 times bypass (normal for UMA systems)*/ + 4 = 4 times bypass (normal for non-UMA systems) + 7 = 7 times bypass (normal for UMA systems)*/ #define NV_RDWRQBYP 8 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2=8 times (normal for non-UMA systems) - 3=16 times (normal for UMA systems)*/ + 2 = 8 times (normal for non-UMA systems) + 3 = 16 times (normal for UMA systems)*/
/*Dram Timing*/ #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0=Auto, no user limit - 1=Auto, user limit provided in NV_MemCkVal - 2=Manual, user value provided in NV_MemCkVal*/ + 0 = Auto, no user limit + 1 = Auto, user limit provided in NV_MemCkVal + 2 = Manual, user value provided in NV_MemCkVal*/ #define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0=200MHz - 1=266MHz - 2=333MHz - 3=400MHz*/ + 0 = 200MHz + 1 = 266MHz + 2 = 333MHz + 3 = 400MHz*/
/*Dram Configuration*/ #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0=normal - 1=enable all memclocks*/ + 0 = normal + 1 = enable all memclocks*/ #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0=Exit current node init if any DIMM has SPD checksum error - 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ + 0 = Exit current node init if any DIMM has SPD checksum error + 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0=skip DQS training - 1=perform DQS training*/ + 0 = skip DQS training + 1 = perform DQS training*/ #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits) - 0=disable (normal) - 1=enable (4 beat burst when width is 64-bits)*/ + 0 = disable (normal) + 1 = enable (4 beat burst when width is 64-bits)*/
/*Dram Power*/ #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0=per Channel control - 1=per Chip select control*/ + 0 = per Channel control + 1 = per Chip select control*/ #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/
/*Memory Map/Mgt.*/ #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) @@ -936,8 +936,8 @@ struct amd_s3_persistent_data { #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) NV_BottomUMA[7:0]=Addr[31:24]*/ #define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0=disable - 1=enable */ + 0 = disable + 1 = enable */
/*ECC*/ #define NV_ECC 50 /* Dram ECC enable*/ @@ -949,13 +949,13 @@ struct amd_s3_persistent_data { #define NV_L3BKScrub 57 /* L3 ECC Background Scrubber CTL*/ #define NV_DCBKScrub 58 /* DCache ECC Background Scrubber CTL*/ #define NV_CS_SpareCTL 59 /* Chip Select Spare Control bit 0: - 0=disable Spare - 1=enable Spare */ + 0 = disable Spare + 1 = enable Spare */ /* Chip Select Spare Control bit 1-4: Reserved, must be zero*/ #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_Unganged 62
#define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index a7fac8f..1b20aa4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -57,7 +57,7 @@ static u32 bsr(u32 x) u8 i; u32 ret = 0;
- for (i=31; i>0; i--) { + for (i = 31; i>0; i--) { if (x & (1<<i)) { ret = i; break; @@ -73,7 +73,7 @@ static u32 bsf(u32 x) u8 i; u32 ret = 32;
- for (i=0; i<32; i++) { + for (i = 0; i < 32; i++) { if (x & (1<<i)) { ret = i; break; @@ -301,7 +301,7 @@ static u32 stream_to_int(u8 *p)
val = 0;
- for (i=3; i>=0; i--) { + for (i = 3; i >= 0; i--) { val <<= 8; valx = *(p+i); val |= valx; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c index 6c25f2c..ef8cb48 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c @@ -33,8 +33,8 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
/* call back to wrapper not needed ManualChannelInterleave_D(); */ /* call back - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv);*/ /* override interleave */ - /* Manually set: typ=5, otherwise typ=7. */ - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ=5: Hash*: exclusive OR of address bits[20:16, 6]. */ + /* Manually set: typ = 5, otherwise typ = 7. */ + DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ = 5: Hash*: exclusive OR of address bits[20:16, 6]. */
if (DctSelIntLvAddr & 1) { DctSelIntLvAddr >>= 1; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 06a70e6..56fe248 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -252,7 +252,7 @@ static void SetEccDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, pDCTstat->Channel = channel; /* Channel A or B */ pDCTstat->Direction = direction; /* Read or write */ CalcEccDQSPos_D(pMCTstat, pDCTstat, pDCTstat->CH_EccDQSLike[channel], pDCTstat->CH_EccDQSScale[channel], ChipSel); - print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); + print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); pDCTstat->ByteLane = 8; StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel); @@ -493,7 +493,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, }
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 14 TestAddr ", TestAddr, 4); - SetUpperFSbase(TestAddr); /* fs:eax=far ptr to target */ + SetUpperFSbase(TestAddr); /* fs:eax = far ptr to target */
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 12 Receiver ", Receiver, 2);
@@ -556,7 +556,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, ResetTargetWTIO_D();
/* Read and compare pattern */ - bytelane_test_results &= (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0=fail, 1=pass */ + bytelane_test_results &= (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0 = fail, 1 = pass */
/* If all lanes have already failed testing bypass remaining re-read attempt(s) */ if (bytelane_test_results == 0x0) @@ -650,7 +650,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, ResetTargetWTIO_D();
/* Read and compare pattern from the base test address */ - bytelane_test_results = (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0=fail, 1=pass */ + bytelane_test_results = (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0 = fail, 1 = pass */
/* Store any lanes that passed testing for later use */ for (lane = 0; lane < 8; lane++) @@ -814,7 +814,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); } @@ -1583,7 +1583,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); } @@ -1843,7 +1843,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); } @@ -1890,11 +1890,11 @@ static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); if (pDCTstat->Status & (1<<SB_128bitmode)) { pDCTstat->Pattern = 1; /* 18 cache lines, alternating qwords */ - for (i=0; i<16*18; i++) + for (i = 0; i < 16*18; i++) buf[i] = TestPatternJD1b_D[i]; } else { pDCTstat->Pattern = 0; /* 9 cache lines, sequential qwords */ - for (i=0; i<16*9; i++) + for (i = 0; i < 16*9; i++) buf[i] = TestPatternJD1a_D[i]; } pDCTstat->PtrPatternBufA = (u32)buf; @@ -2058,7 +2058,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat }
bytelane = 0; /* bytelane counter */ - bitmap = 0xFFFF; /* bytelane test bitmap, 1=pass */ + bitmap = 0xFFFF; /* bytelane test bitmap, 1 = pass */ MEn1Results = 0xFFFF; BeatCnt = 0; for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ @@ -2349,7 +2349,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat,
val &= ~0xe007c01f;
- /* unganged mode DCT0+DCT1, sys addr of DCT1=node + /* unganged mode DCT0+DCT1, sys addr of DCT1 = node * base+DctSelBaseAddr+local ca base*/ if ((Channel) && (pDCTstat->GangedMode == 0) && ( pDCTstat->DIMMValidDCT[0] > 0)) { reg = 0x110; @@ -2365,7 +2365,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, val += dword; } } else { - /* sys addr=node base+local cs base */ + /* sys addr = node base+local cs base */ val += pDCTstat->DCTSysBase;
/* New stuff */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 5d31849..07f1d8d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -36,7 +36,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); * * Conditions for setting background scrubber. * 1. node is present - * 2. node has dram functioning (WE=RE=1) + * 2. node has dram functioning (WE = RE = 1) * 3. all eccdimms (or bit 17 of offset 90,fn 2) * 4. no chip-select gap exists * @@ -353,7 +353,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) } else { ch_end = 2; } - for (i=0; i<ch_end; i++) { + for (i = 0; i < ch_end; i++) { if (pDCTstat->DIMMValidDCT[i] > 0){ reg = 0x90; /* Dram Config Low */ val = Get_NB32_DCT(dev, i, reg); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c index 8ed2bef..fd32c40 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c @@ -34,11 +34,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
/* Set temporary top of memory from Node structure data. * Adjust temp top of memory down to accommodate 32-bit IO space. - * Bottom40bIO=top of memory, right justified 8 bits + * Bottom40bIO = top of memory, right justified 8 bits * (defines dram versus IO space type) - * Bottom32bIO=sub 4GB top of memory, right justified 8 bits + * Bottom32bIO = sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) - * Cache32bTOP=sub 4GB top of WB cacheable memory, + * Cache32bTOP = sub 4GB top of WB cacheable memory, * right justified 8 bits */
@@ -82,8 +82,8 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, */ addr = 0x204; /* MTRR phys base 2*/ /* use TOP_MEM as limit*/ - /* Limit=TOP_MEM|TOM2*/ - /* Base=0*/ + /* Limit = TOP_MEM|TOM2*/ + /* Base = 0*/ printk(BIOS_DEBUG, "\t CPUMemTyping: Cache32bTOP:%x\n", Cache32bTOP); SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); /* Base */ @@ -112,10 +112,10 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, addr = 0xC0010010; /* SYS_CFG */ _RDMSR(addr, &lo, &hi); if (Bottom40bIO) { - lo |= (1<<21); /* MtrrTom2En=1 */ + lo |= (1<<21); /* MtrrTom2En = 1 */ lo |= (1<<22); /* Tom2ForceMemTypeWB */ } else { - lo &= ~(1<<21); /* MtrrTom2En=0 */ + lo &= ~(1<<21); /* MtrrTom2En = 0 */ lo &= ~(1<<22); /* Tom2ForceMemTypeWB */ } _WRMSR(addr, lo, hi); @@ -146,7 +146,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) * next set bit in a forward or backward sequence of bits (as a function * of the Limit). We start with the ascending path, to ensure that * regions are naturally aligned, then we switch to the descending path - * to maximize MTRR usage efficiency. Base=0 is a special case where we + * to maximize MTRR usage efficiency. Base = 0 is a special case where we * start with the descending path. Correct Mask for region is * 2comp(Size-1)-1, which is 2comp(Limit-Base-1)-1 */ @@ -172,14 +172,14 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) curSize = valx; valx += curBase; } - curLimit = valx; /*eax=curBase, edx=curLimit*/ + curLimit = valx; /*eax = curBase, edx = curLimit*/ valx = val>>24; val <<= 8;
/* now program the MTRR */ val |= MtrrType; /* set cache type (UC or WB)*/ _WRMSR(addr, val, valx); /* prog. MTRR with current region Base*/ - val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask=2comp(Size-1)-1*/ + val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask = 2comp(Size-1)-1*/ valx = (val >> 24) | (0xff00); /* GH have 48 bits addr */ val <<= 8; val |= ( 1 << 11); /* set MTRR valid*/ @@ -213,9 +213,9 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat /*====================================================================== * Adjust temp top of memory down to accommodate UMA memory start *======================================================================*/ - /* Bottom32bIO=sub 4GB top of memory, right justified 8 bits + /* Bottom32bIO = sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) - * Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 8 bits */ + * Cache32bTOP = sub 4GB top of WB cacheable memory, right justified 8 bits */
Bottom32bIO = pMCTstat->Sub4GCacheTop >> 8;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c index 9a769ad..8ac176c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c @@ -139,7 +139,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, if (DoIntlv) { MCTMemClr_D(pMCTstat, pDCTstatA); /* Program Interleaving enabled on Node 0 map only.*/ - MemSize0 <<= bsf(Nodes); /* MemSize=MemSize*2 (or 4, or 8) */ + MemSize0 <<= bsf(Nodes); /* MemSize = MemSize*2 (or 4, or 8) */ Dct0MemSize <<= bsf(Nodes); MemSize0 += HWHoleSz; Base = ((Nodes - 1) << 8) | 3; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c index 951a712..ac24c6d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c @@ -336,14 +336,14 @@ void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat, printk(BIOS_SPEW, "%s: F2xA8: %08x\n", __func__, val);
if (is_fam15h()) { - for (cw=0; cw <=15; cw ++) { + for (cw = 0; cw <=15; cw ++) { val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), cw); mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val); if ((cw == 2) || (cw == 8) || (cw == 10)) precise_ndelay_fam15(pMCTstat, 6000); } } else { - for (cw=0; cw <=15; cw ++) { + for (cw = 0; cw <=15; cw ++) { mct_Wait(1600); val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), cw); mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index 670d640..18af172 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -912,7 +912,7 @@ static u32 mct_MR1(struct MCTStatStruc *pMCTstat, /* program MrsAddress[11]=TDQS: based on F2x[1,0]94[RDqsEn] */ if (Get_NB32_DCT(dev, dct, 0x94) & (1 << RDqsEn)) { u8 bit; - /* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */ + /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */ bit = (ret >> 21) << 1; if ((dct & 1) != 0) bit ++; @@ -1063,7 +1063,7 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct) printk(BIOS_DEBUG, "%s: Start\n", __func__);
/*1.Program MrsAddress[10]=1 - 2.Set SendZQCmd=1 + 2.Set SendZQCmd = 1 */ dword = Get_NB32_DCT(dev, dct, 0x7C); dword &= ~0xFFFFFF; @@ -1071,7 +1071,7 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct) dword |= 1 << SendZQCmd; Set_NB32_DCT(dev, dct, 0x7C, dword);
- /* Wait for SendZQCmd=0 */ + /* Wait for SendZQCmd = 0 */ do { dword = Get_NB32_DCT(dev, dct, 0x7C); } while (dword & (1 << SendZQCmd)); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 8024179..3b57cb9 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -76,7 +76,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, p_A = (u32 *)SetupDqsPattern_1PassB(pass); p_B = (u32 *)SetupDqsPattern_1PassA(pass);
- for (i=0;i<16;i++) { + for (i = 0; i < 16; i++) { buf_a[i] = p_A[i]; buf_b[i] = p_B[i]; } @@ -996,7 +996,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } @@ -1013,10 +1013,10 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); - for (ReceiverDTD = 0; ReceiverDTD<8; ReceiverDTD+=2) { + for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); } @@ -1510,7 +1510,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } @@ -1527,10 +1527,10 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); - for (ReceiverDTD = 0; ReceiverDTD<8; ReceiverDTD+=2) { + for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); } @@ -1730,7 +1730,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "TrainMaxRdLatency: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } @@ -1766,7 +1766,7 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat) ch_end = 2; }
- for (ch=0; ch<ch_end; ch++) { + for (ch = 0; ch < ch_end; ch++) { reg = 0x78; val = Get_NB32_DCT(dev, ch, reg); val &= ~(1 << DqsRcvEnTrain); @@ -1800,14 +1800,14 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, }
/* DimmOffset not needed for CH_D_B_RCVRDLY array */ - for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; }
- /* if flag=0, set DqsRcvEn value to reg. */ + /* if flag = 0, set DqsRcvEn value to reg. */ /* get the register index from table */ index = Table_DQSRcvEn_Offset[i >> 1]; index += Addl_Index; /* DIMMx DqsRcvEn byte0 */ @@ -1852,7 +1852,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); if ((package_type == PT_L1) /* Socket F (1207) */ || (package_type == PT_M2) /* Socket AM3 */ - || (package_type == PT_S1)) { /* Socket S1g<x> */ + || (package_type == PT_S1)) { /* Socket S1g < x> */ cpu_val_n = 10; cpu_val_p = 11; } else { @@ -1950,7 +1950,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, * Read Position is 1/2 Memclock Delay */ u8 i; - for (i=0;i<2; i++){ + for (i = 0; i < 2; i++){ InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -1972,8 +1972,8 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
/* FIXME: add Cx support */ dword = 0x00000000; - for (i=1; i<=3; i++) { - for (j=0; j<dn; j++) + for (i = 1; i <= 3; i++) { + for (j = 0; j < dn; j++) /* DIMM0 Write Data Timing Low */ /* DIMM0 Write ECC Timing */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, i + 0x100 * j, dword); @@ -1981,14 +1981,14 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
/* errata #180 */ dword = 0x2f2f2f2f; - for (i=5; i<=6; i++) { - for (j=0; j<dn; j++) + for (i = 5; i <= 6; i++) { + for (j = 0; j < dn; j++) /* DIMM0 Read DQS Timing Control Low */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, i + 0x100 * j, dword); }
dword = 0x0000002f; - for (j=0; j<dn; j++) + for (j = 0; j < dn; j++) /* DIMM0 Read DQS ECC Timing Control */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, 7 + 0x100 * j, dword); } @@ -2087,7 +2087,7 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, if (!pDCTstat->NodePresent) break; if (pDCTstat->DCTSysLimit) { - for (i=0; i<2; i++) + for (i = 0; i < 2; i++) CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i); } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c index d535735..30cf19b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -49,7 +49,7 @@ static u16 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel MaxValue = 0; p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1];
- for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ val = p[i]; /* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c index 2f4d4da..2bd5e73 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c @@ -58,7 +58,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 bn; bn = 8;
- for ( i=0;i<bn; i++) { + for ( i = 0; i < bn; i++) { val = p[i];
if (val > max) { @@ -91,7 +91,7 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, /* FIXME: which byte? */ p_1 = pDCTstat->B_RCVRDLY_1; /* p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ - for (i=0; i<bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ if (val != (RcvrEnDlyLimit - 1)) { @@ -111,7 +111,7 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } } else { - for (i=0; i < bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ /* val += Pass1MemClkDly; */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 15eb67e..e483253 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -190,7 +190,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } @@ -207,7 +207,7 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat,
if (pDCTstat->GangedMode) { Channel = 0; /* for safe */ - for (i=0; i<2; i++) + for (i = 0; i < 2; i++) pDCTstat->CH_MaxRdLat[i][0] = MaxRdLatVal; } else { pDCTstat->CH_MaxRdLat[Channel][0] = MaxRdLatVal; @@ -239,7 +239,7 @@ static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr) addr_lo = addr<<8;
_EXECFENCE; - for (i=0; i<(16*3); i++) { + for (i = 0; i<(16*3); i++) { val = read32_fs(addr_lo); val_test = test_buf[i];
@@ -284,8 +284,8 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, *valid = 0;
for (ch = ch_start; ch < ch_end; ch++) { - for (d=0; d<4; d++) { - for (Byte = 0; Byte<bn; Byte++) { + for (d = 0; d < 4; d++) { + for (Byte = 0; Byte < bn; Byte++) { u8 tmp; tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; if (tmp>Max) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index 44ea6e8..47c5004 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -426,7 +426,7 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, } }
- /* wait for 500 MCLKs after ExitSelfRef, 500*2.5ns=1250ns */ + /* wait for 500 MCLKs after ExitSelfRef, 500*2.5ns = 1250ns */ mct_Wait(250);
if (pDCTstat->Status & (1 << SB_Registered)) { @@ -474,9 +474,9 @@ void Restore_OnDimmMirror(struct MCTStatStruc *pMCTstat, { if (pDCTstat->LogicalCPUID & (AMD_DR_Bx /* | AMD_RB_C0 */)) { /* We dont support RB-C0 now */ if (pDCTstat->MirrPresU_NumRegR & 0x55) - Modify_OnDimmMirror(pDCTstat, 0, 1); /* dct=0, set */ + Modify_OnDimmMirror(pDCTstat, 0, 1); /* dct = 0, set */ if (pDCTstat->MirrPresU_NumRegR & 0xAA) - Modify_OnDimmMirror(pDCTstat, 1, 1); /* dct=1, set */ + Modify_OnDimmMirror(pDCTstat, 1, 1); /* dct = 1, set */ } } void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat, @@ -484,8 +484,8 @@ void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat, { if (pDCTstat->LogicalCPUID & (AMD_DR_Bx /* | AMD_RB_C0 */)) { /* We dont support RB-C0 now */ if (pDCTstat->MirrPresU_NumRegR & 0x55) - Modify_OnDimmMirror(pDCTstat, 0, 0); /* dct=0, clear */ + Modify_OnDimmMirror(pDCTstat, 0, 0); /* dct = 0, clear */ if (pDCTstat->MirrPresU_NumRegR & 0xAA) - Modify_OnDimmMirror(pDCTstat, 1, 0); /* dct=1, clear */ + Modify_OnDimmMirror(pDCTstat, 1, 0); /* dct = 1, clear */ } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index 5c30bc5..098948a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -140,15 +140,15 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT */ if (dct) { - Addl_Data_Offset=0x198; - Addl_Data_Port=0x19C; + Addl_Data_Offset = 0x198; + Addl_Data_Port = 0x19C; } else { - Addl_Data_Offset=0x98; - Addl_Data_Port=0x9C; + Addl_Data_Offset = 0x98; + Addl_Data_Port = 0x9C; } - Addr=0x0D00000C; + Addr = 0x0D00000C; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, DctAccessDone, DctAccessDone)) == 0); @@ -157,7 +157,7 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT Value = bitTestReset(Value, 4); /* for x8 only */ Value = bitTestReset(Value, 5); /* for hardware WL training */ AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); - Addr=0x4D030F0C; + Addr = 0x4D030F0C; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, DctAccessDone, DctAccessDone)) == 0); @@ -453,22 +453,22 @@ static uint16_t unbuffered_dimm_nominal_termination_emrs(uint8_t number_of_dimms
if (number_of_dimms == 1) { if (MaxDimmsInstallable < 3) { - term = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */ + term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */ } else { if (rank_count == 1) { - term = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */ + term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */ } else { if (rank == 0) - term = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */ + term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */ else - term = 0x00; /* Rtt_Nom=OFF */ + term = 0x00; /* Rtt_Nom = OFF */ } } } else { if (frequency_index < 5) - term = 0x0044; /* Rtt_Nom=RZQ/6=40 Ohm */ + term = 0x0044; /* Rtt_Nom = RZQ/6 = 40 Ohm */ else - term = 0x0204; /* Rtt_Nom=RZQ/8=30 Ohm */ + term = 0x0204; /* Rtt_Nom = RZQ/8 = 30 Ohm */ }
return term; @@ -482,15 +482,15 @@ static uint16_t unbuffered_dimm_dynamic_termination_emrs(uint8_t number_of_dimms
if (number_of_dimms == 1) { if (MaxDimmsInstallable < 3) { - term = 0x00; /* Rtt_WR=off */ + term = 0x00; /* Rtt_WR = off */ } else { if (rank_count == 1) - term = 0x00; /* Rtt_WR=off */ + term = 0x00; /* Rtt_WR = off */ else - term = 0x200; /* Rtt_WR=RZQ/4=60 Ohm */ + term = 0x200; /* Rtt_WR = RZQ/4 = 60 Ohm */ } } else { - term = 0x400; /* Rtt_WR=RZQ/2=120 Ohm */ + term = 0x400; /* Rtt_WR = RZQ/2 = 120 Ohm */ }
return term; @@ -558,7 +558,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, tempW = mct_MR1(pMCTstat, pDCTstat, dct, dimm*2+rank) & 0xffff; tempW &= ~(0x0244); } else { - /* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */ + /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */ tempW2 = get_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, DRAM_CONFIG_HIGH, RDqsEn, RDqsEn); if (tempW2) @@ -618,7 +618,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, }
/* Apply Rtt_Nom to the MRS control word */ - tempW=tempW|tempW1; + tempW = tempW|tempW1;
/* All ranks of the target DIMM are set to write levelization mode. */ if (wl) @@ -702,8 +702,8 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, {tempW = bitTestSet(tempW, 7);} if (bitTest(tempW1,18)) {tempW = bitTestSet(tempW, 6);} - /* tempW=tempW|(((tempW1>>20)&0x7)<<3); */ - tempW=tempW|((tempW1&0x00700000)>>17); + /* tempW = tempW|(((tempW1>>20)&0x7)<<3); */ + tempW = tempW|((tempW1&0x00700000)>>17); /* workaround for DR-B0 */ if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED])) tempW+=0x8; @@ -720,7 +720,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, }
/* Apply Rtt_WR to the MRS control word */ - tempW=tempW|tempW1; + tempW = tempW|tempW1; tempW = swapAddrBits_wl(pDCTstat, dct, tempW); if (is_fam15h()) set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, @@ -779,14 +779,14 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, /* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required * DDR3-defined function for write levelization. */ - tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0, Level=0, Qoff=0 */ + tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0, Level = 0, Qoff = 0 */
/* Retrieve normal settings of the MRS control word and clear Rtt_Nom */ if (is_fam15h()) { tempW = mct_MR1(pMCTstat, pDCTstat, dct, currDimm*2+rank) & 0xffff; tempW &= ~(0x0244); } else { - /* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */ + /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */ tempW2 = get_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, DRAM_CONFIG_HIGH, RDqsEn, RDqsEn); if (tempW2) @@ -811,7 +811,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, }
/* Apply Rtt_Nom to the MRS control word */ - tempW=tempW|tempW1; + tempW = tempW|tempW1;
/* Program MrsAddress[5,1]=output driver impedance control (DIC) */ if (is_fam15h()) { @@ -877,8 +877,8 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, {tempW = bitTestSet(tempW, 7);} if (bitTest(tempW1,18)) {tempW = bitTestSet(tempW, 6);} - /* tempW=tempW|(((tempW1>>20)&0x7)<<3); */ - tempW=tempW|((tempW1&0x00700000)>>17); + /* tempW = tempW|(((tempW1>>20)&0x7)<<3); */ + tempW = tempW|((tempW1&0x00700000)>>17); /* workaround for DR-B0 */ if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED])) tempW+=0x8; @@ -895,7 +895,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, }
/* Apply Rtt_WR to the MRS control word */ - tempW=tempW|tempW1; + tempW = tempW|tempW1; tempW = swapAddrBits_wl(pDCTstat, dct, tempW); if (is_fam15h()) set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, @@ -939,7 +939,7 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui sMCTStruct *pMCTData = pDCTstat->C_MCTPtr; sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct];
- u8 WrLvOdt1=0; + u8 WrLvOdt1 = 0;
if (is_fam15h()) { /* On Family15h processors, the value for the specific CS being targetted @@ -1045,25 +1045,25 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui } else { - /* Program WrLvOdtEn=1 through set bit 12 of D3CSODT reg offset 0 for Rev.B */ + /* Program WrLvOdtEn = 1 through set bit 12 of D3CSODT reg offset 0 for Rev.B */ if (dct) { - Addl_Data_Offset=0x198; - Addl_Data_Port=0x19C; + Addl_Data_Offset = 0x198; + Addl_Data_Port = 0x19C; } else { - Addl_Data_Offset=0x98; - Addl_Data_Port=0x9C; + Addl_Data_Offset = 0x98; + Addl_Data_Port = 0x9C; } - Addr=0x0D008000; + Addr = 0x0D008000; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, DctAccessDone, DctAccessDone)) == 0); AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); Value = bitTestSet(Value, 12); AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); - Addr=0x4D088F00; + Addr = 0x4D088F00; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, DctAccessDone, DctAccessDone)) == 0); @@ -1371,7 +1371,7 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 while (ByteLane < lane_count) { /* This subtract 0xC workaround might be temporary. */ - if ((pDCTData->WLPass==2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) { + if ((pDCTData->WLPass == 2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) { tempW = (pDCTData->WLGrossDelay[index+ByteLane] << 5) | pDCTData->WLFineDelay[index+ByteLane]; tempW -= 0xC; pDCTData->WLGrossDelay[index+ByteLane] = (u8)(tempW >> 5); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 6589a39..97cadcb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -351,12 +351,12 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x11c = pci_read_config32(dev_fn2, 0x11c); data->f2x1b0 = pci_read_config32(dev_fn2, 0x1b0); data->f3x44 = pci_read_config32(dev_fn3, 0x44); - for (i=0; i<16; i++) { + for (i = 0; i < 16; i++) { data->msr0000020[i] = rdmsr_uint64_t(0x00000200 | i); } data->msr00000250 = rdmsr_uint64_t(0x00000250); data->msr00000258 = rdmsr_uint64_t(0x00000258); - for (i=0; i<8; i++) + for (i = 0; i < 8; i++) data->msr0000026[i] = rdmsr_uint64_t(0x00000260 | (i + 8)); data->msr000002ff = rdmsr_uint64_t(0x000002ff); data->msrc0010010 = rdmsr_uint64_t(0xc0010010); @@ -393,7 +393,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x204 = read_config32_dct(dev_fn2, node, channel, 0x204); data->f2x208 = read_config32_dct(dev_fn2, node, channel, 0x208); data->f2x20c = read_config32_dct(dev_fn2, node, channel, 0x20c); - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) data->f2x210[i] = read_config32_dct_nbpstate(dev_fn2, node, channel, i, 0x210); data->f2x214 = read_config32_dct(dev_fn2, node, channel, 0x214); data->f2x218 = read_config32_dct(dev_fn2, node, channel, 0x218); @@ -407,7 +407,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da
data->f2x9cx0d0fe003 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe003); data->f2x9cx0d0fe013 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe013); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_8_0_1f[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f001f | (i << 8)); data->f2x9cx0d0f201f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f201f); data->f2x9cx0d0f211f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f211f); @@ -419,11 +419,11 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0fc11f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc11f); data->f2x9cx0d0fc21f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc21f); data->f2x9cx0d0f4009 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f4009); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_8_0_02[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0002 | (i << 8)); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_8_0_06[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0006 | (i << 8)); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_8_0_0a[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f000a | (i << 8));
data->f2x9cx0d0f2002 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2002); @@ -450,7 +450,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0fc031 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc031); data->f2x9cx0d0fc131 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc131); data->f2x9cx0d0fc231 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc231); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_0_f_31[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0031 | (i << 8));
data->f2x9cx0d0f8021 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8021); @@ -463,8 +463,8 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x94 = read_config32_dct(dev_fn2, node, channel, 0x94);
/* Stage 6 */ - for (i=0; i<9; i++) - for (j=0; j<3; j++) + for (i = 0; i < 9; i++) + for (j = 0; j < 3; j++) data->f2x9cx0d0f0_f_8_0_0_8_4_0[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4)); data->f2x9cx00 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x00); data->f2x9cx0a = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0a); @@ -478,33 +478,33 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0fe007 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe007);
/* Stage 10 */ - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) data->f2x9cx10[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x10 + i); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) data->f2x9cx20[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x20 + i); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) data->f2x9cx3_0_0_3_1[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, (0x01 + i) + (0x100 * j)); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) data->f2x9cx3_0_0_7_5[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, (0x05 + i) + (0x100 * j)); data->f2x9cx0d = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_f_0_13[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0013 | (i << 8)); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_f_0_30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0030 | (i << 8)); - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) data->f2x9cx0d0f2_f_0_30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2030 | (i << 8)); - for (i=0; i<2; i++) - for (j=0; j<3; j++) + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) data->f2x9cx0d0f8_8_4_0[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4)); data->f2x9cx0d0f812f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f812f);
/* Stage 11 */ if (IS_ENABLED(CONFIG_DIMM_DDR3)) { - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) data->f2x9cx30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x30 + i); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) data->f2x9cx40[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x40 + i); }
@@ -599,28 +599,28 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste continue;
/* Restore training parameters */ - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x01 + i) + (0x100 * j), data->f2x9cx3_0_0_3_1[i][j]); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x05 + i) + (0x100 * j), data->f2x9cx3_0_0_7_5[i][j]);
- for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x10 + i, data->f2x9cx10[i]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]);
if (IS_ENABLED(CONFIG_DIMM_DDR3)) { - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x40 + i, data->f2x9cx40[i]); }
/* Restore MaxRdLatency */ if (is_fam15h()) { - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) write_config32_dct_nbpstate(PCI_DEV(0, 0x18 + node, 2), node, channel, i, 0x210, data->f2x210[i]); } else { write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x78, data->f2x78); @@ -682,7 +682,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x11c, data->f2x11c); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x1b0, data->f2x1b0); write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, channel, 0x44, data->f3x44); - for (i=0; i<16; i++) { + for (i = 0; i < 16; i++) { wrmsr_uint64_t(0x00000200 | i, data->msr0000020[i]); } wrmsr_uint64_t(0x00000250, data->msr00000250); @@ -692,7 +692,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste * destroying CAR while still executing from CAR! * For now, skip restoration... */ - // for (i=0; i<8; i++) + // for (i = 0; i < 8; i++) // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); wrmsr_uint64_t(0x000002ff, data->msr000002ff); wrmsr_uint64_t(0xc0010010, data->msrc0010010); @@ -760,7 +760,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x204, data->f2x204); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x208, data->f2x208); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x20c, data->f2x20c); - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) write_config32_dct_nbpstate(PCI_DEV(0, 0x18 + node, 2), node, channel, i, 0x210, data->f2x210[i]); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x214, data->f2x214); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x218, data->f2x218); @@ -773,7 +773,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x240, data->f2x240);
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe013, data->f2x9cx0d0fe013); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f001f | (i << 8), data->f2x9cx0d0f0_8_0_1f[i]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f201f, data->f2x9cx0d0f201f); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f211f, data->f2x9cx0d0f211f); @@ -795,7 +795,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc031, data->f2x9cx0d0fc031); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc131, data->f2x9cx0d0fc131); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc231, data->f2x9cx0d0fc231); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0031 | (i << 8), data->f2x9cx0d0f0_0_f_31[i]);
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8021, data->f2x9cx0d0f8021); @@ -899,8 +899,8 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste if (!persistent_data->node[node].node_present) continue;
- for (i=0; i<9; i++) - for (j=0; j<3; j++) + for (i = 0; i < 9; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4), data->f2x9cx0d0f0_f_8_0_0_8_4_0[i][j]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x00, data->f2x9cx00); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0a, data->f2x9cx0a); @@ -920,11 +920,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste dword |= (0x3 << 13); /* DisAutoComp, DisablePredriverCal = 1 */ write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe003, dword);
- for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0006 | (i << 8), data->f2x9cx0d0f0_8_0_06[i]); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f000a | (i << 8), data->f2x9cx0d0f0_8_0_0a[i]); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0002 | (i << 8), (0x8000 | data->f2x9cx0d0f0_8_0_02[i]));
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8006, data->f2x9cx0d0f8006); @@ -1024,25 +1024,25 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste if (!persistent_data->node[node].node_present) continue;
- for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x10 + i, data->f2x9cx10[i]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x01 + i) + (0x100 * j), data->f2x9cx3_0_0_3_1[i][j]); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x05 + i) + (0x100 * j), data->f2x9cx3_0_0_7_5[i][j]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d, data->f2x9cx0d); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0013 | (i << 8), data->f2x9cx0d0f0_f_0_13[i]); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0030 | (i << 8), data->f2x9cx0d0f0_f_0_30[i]); - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f2030 | (i << 8), data->f2x9cx0d0f2_f_0_30[i]); - for (i=0; i<2; i++) - for (j=0; j<3; j++) + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4), data->f2x9cx0d0f8_8_4_0[i][j]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f812f, data->f2x9cx0d0f812f); } @@ -1056,9 +1056,9 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste if (!persistent_data->node[node].node_present) continue;
- for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x40 + i, data->f2x9cx40[i]); } } diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 143468a..cc37785 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -481,7 +481,7 @@ static void vErratum372(struct DCTStatStruc *pDCTstat) int nbPstate1supported = !(msr.hi & (1 << (NB_GfxNbPstateDis -32)));
// is this the right way to check for NB pstate 1 or DDR3-1333 ? - if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported)) + if (((pDCTstat->PresetmaxFreq == 1333)||(nbPstate1supported)) &&(!pDCTstat->GangedMode)) { /* DisableCf8ExtCfg */ msr.hi &= ~(3 << (51 - 32)); @@ -491,7 +491,7 @@ static void vErratum372(struct DCTStatStruc *pDCTstat)
static void vErratum414(struct DCTStatStruc *pDCTstat) { - int dct=0; + int dct = 0; for (; dct < 2 ; dct++) { int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); int powerDown = dRAMConfigHi & (1 << PowerDownEn ); diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index c10428d..9581527 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -78,7 +78,7 @@ static void rd890_enable(device_t dev) 0, (devfn >> 3), (devfn & 0x07), dev->enabled);
/* we only do this once */ - if (devfn==0) { + if (devfn == 0) { /* CIMX configuration defualt initialize */ rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); if (gConfig.StandardHeader.CalloutPtr != NULL) { diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index f21d717..29d4689 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -35,24 +35,24 @@ struct gliutable };
struct gliutable gliu0table[] = { - {.desc_name=GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ - {.desc_name=GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ - {.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ - {.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, - {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, + {.desc_name = GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name = GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ + {.desc_name = GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ + {.desc_name = GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, + {.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, };
struct gliutable gliu1table[] = { - {.desc_name=GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ - {.desc_name=GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */ - {.desc_name=GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ - {.desc_name=GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, - {.desc_name=GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ - {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, + {.desc_name = GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name = GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */ + {.desc_name = GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ + {.desc_name = GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, + {.desc_name = GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ + {.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, };
struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 }; @@ -64,51 +64,51 @@ struct msrinit };
struct msrinit ClockGatingDefault[] = { - {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, + {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, /* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */ - {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, - {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ - {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, - {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, - {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */ + {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, + {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, + {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */ + {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, + {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}}, + {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* Always on */ {0xffffffff, {0xffffffff, 0xffffffff}}, };
/* All On */ struct msrinit ClockGatingAllOn[] = { - {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {VG_GLD_MSR_PM, {.hi=0x00, .lo=0x00}}, - {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x000000001}}, - {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, + {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {VG_GLD_MSR_PM, {.hi = 0x00, .lo = 0x00}}, + {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x000000001}}, + {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, {0xffffffff, {0xffffffff, 0xffffffff}}, };
/* Performance */ struct msrinit ClockGatingPerformance[] = { - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ - {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, - {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, - {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, + {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */ + {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, + {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}}, + {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, {0xffffffff, {0xffffffff, 0xffffffff}}, };
/* SET GeodeLink PRIORITY */ struct msrinit GeodeLinkPriorityTable[] = { - {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */ - {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */ - {VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority. */ - {GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority. */ - {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID */ - {GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID */ - {FG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* FG PID */ + {CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}}, /* CPU Priority. */ + {DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}}, /* DF Priority. */ + {VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}}, /* VG Primary and Secondary Priority. */ + {GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}}, /* Graphics Priority. */ + {GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0027}}, /* GLPCI Priority + PID */ + {GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}}, /* GLCP Priority + PID */ + {FG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}}, /* FG PID */ {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */ };
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index db10138..a6ee0b7 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -130,7 +130,7 @@ static void auto_size_dimm(unsigned int dimm) * Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes), * so lower 3 address bits are dont_cares. So from the table above, * it's easier to see what the old code is doing: if for example, - * #col_addr_bits=7(06h), it adds 3 to get 10, then does 2^10=1K. + * #col_addr_bits = 7(06h), it adds 3 to get 10, then does 2^10 = 1K. */
spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; @@ -145,7 +145,7 @@ static void auto_size_dimm(unsigned int dimm) if (spd_byte > 4) { /* if the value is above 4 it means >11 col address lines */ spd_byte = 7; /* which means >16k so set to disabled */ } - dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */ + dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k,1 = 2k,2 = 4k,etc */
printk(BIOS_DEBUG, "RDMSR CF07\n"); msr = rdmsr(MC_CF07_DATA); @@ -230,7 +230,7 @@ const uint8_t CASDDR[] = { 5, 5, 2, 6, 0 }; /* 1(1.5), 1.5, 2, 2.5, 0 */ static u8 getcasmap(u32 dimm, u16 glspeed) { u16 dimm_speed; - u8 spd_byte, casmap, casmap_shift=0; + u8 spd_byte, casmap, casmap_shift = 0;
/************************** DIMM0 **********************************/ casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 2ba4a04..a40a628 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -91,7 +91,7 @@ struct msr_defaults { /* 180d is left at default, e0000-fffff is non-cached */ /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ /* we will not set 0x180f, the DMM,yet */ - //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, + //{0x1810, {.hi = 0xee7ff000, .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index c540f9a..6f44f17 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -131,12 +131,12 @@ static void auto_size_dimm(unsigned int dimm) *;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size) *;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size) *;pa 14 13 AP 12 11 10 09 08 07 06 05 04 03 (12 col addr bits = 32K page size) -*; *AP=autoprecharge bit +*; *AP = autoprecharge bit * *;Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes), *;so lower 3 address bits are dont_cares.So from the table above, -*;it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h), -*;it adds 3 to get 10, then does 2^10=1K. Get it?*/ +*;it's easier to see what the old code is doing: if for example,#col_addr_bits = 7(06h), +*;it adds 3 to get 10, then does 2^10 = 1K. Get it?*/
spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; banner("MAXCOLADDR"); @@ -150,7 +150,7 @@ static void auto_size_dimm(unsigned int dimm) if (spd_byte > 5) { /* if the value is above 6 it means >12 address lines */ spd_byte = 7; /* which means >32k so set to disabled */ } - dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */ + dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k,1 = 2k,2 = 4k,etc */
banner("RDMSR CF07"); msr = rdmsr(MC_CF07_DATA); @@ -242,7 +242,7 @@ const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, static u8 getcasmap(u32 dimm, u16 glspeed) { u16 dimm_speed; - u8 spd_byte, casmap, casmap_shift=0; + u8 spd_byte, casmap, casmap_shift = 0;
/************************** DIMM0 **********************************/ casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES); @@ -730,8 +730,8 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) }
/* Set PMode0 Sensitivity Counter */ - msr.lo = 0; /* pmode 0=0 most aggressive */ - msr.hi = 0x200; /* pmode 1=200h */ + msr.lo = 0; /* pmode 0 = 0 most aggressive */ + msr.hi = 0x200; /* pmode 1 = 200h */ wrmsr(MC_CF_PMCTR, msr);
/* Set PMode1 Up delay enable */ diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 0f9e5f5..083458c 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -88,10 +88,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -101,10 +101,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -131,7 +131,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); }
static u32 f1_read_config32(unsigned reg) @@ -619,7 +619,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -687,7 +687,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -1059,7 +1059,7 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
for (j = 0; j <= siblings; j++ ) { @@ -1081,10 +1081,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lapicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lapicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index efee0a4..c45c19c 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -100,10 +100,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -134,7 +134,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); }
static u32 f1_read_config32(unsigned reg) @@ -1059,7 +1059,7 @@ static void cpu_bus_scan(device_t dev) siblings = 0; } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
for (j = 0; j <= siblings; j++ ) { @@ -1081,10 +1081,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 6d5418a..de4e0cb 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -83,7 +83,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 @@ -97,7 +97,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -107,10 +107,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }
@@ -141,7 +141,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); }
static u32 f1_read_config32(unsigned reg) @@ -646,7 +646,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -709,7 +709,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -1090,7 +1090,7 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
for (j = 0; j <= siblings; j++ ) { @@ -1112,10 +1112,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c index d48a089..9d79c9b 100644 --- a/src/northbridge/intel/e7501/debug.c +++ b/src/northbridge/intel/e7501/debug.c @@ -148,7 +148,7 @@ static inline void dump_io_resources(unsigned port) { int i; printk(BIOS_DEBUG, "%04x:\n", port); - for (i=0;i<256;i++) { + for (i = 0; i < 256; i++) { uint8_t val; if ((i & 0x0f) == 0) printk(BIOS_DEBUG, "%02x:", i); @@ -165,7 +165,7 @@ static inline void dump_mem(unsigned start, unsigned end) { unsigned i; printk(BIOS_DEBUG, "dump_mem:"); - for (i=start;i<end;i++) { + for (i = start; i < end; i++) { if ((i & 0xf)==0) printk(BIOS_DEBUG, "\n%08x:", i); printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index 022257c..cb94f84 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -159,7 +159,7 @@ void dump_io_resources(unsigned port)
int i; printk(BIOS_DEBUG, "%04x:\n", port); - for (i=0;i<256;i++) { + for (i = 0; i < 256; i++) { uint8_t val; if ((i & 0x0f) == 0) printk(BIOS_DEBUG, "%02x:", i); @@ -176,7 +176,7 @@ void dump_mem(unsigned start, unsigned end) { unsigned i; printk(BIOS_DEBUG, "dump_mem:"); - for (i=start;i<end;i++) { + for (i = start; i < end; i++) { if ((i & 0xf)==0) printk(BIOS_DEBUG, "\n%08x:", i); printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 259fdd2..8804ce8 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -1710,7 +1710,7 @@ static void sdram_enable(const struct mem_controller *ctrl) /* And for good luck 6 more CBRs */ RAM_DEBUG_MESSAGE("Ram Enable 8\n"); int i; - for (i=0; i<8; i++) + for (i = 0; i < 8; i++) do_ram_command(RAM_COMMAND_CBR, 0);
/* 9 mode register set */ @@ -1823,7 +1823,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) /* Disable legacy MMIO (0xC0000-0xEFFFF is DRAM) */ int i; pci_write_config8(MCHDEV, PAM_0, 0x30); - for (i=1; i<=6; i++) + for (i = 1; i <= 6; i++) pci_write_config8(MCHDEV, PAM_0 + i, 0x33);
/* Conservatively say each row has 64MB of ram, we will fix this up later diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 2ac1a23..6a33eda 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -170,7 +170,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { - *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + *(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
if (Status == 0xFFFFFFFF) { soft_reset(); diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index b2ae3c4..4cb901a 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -88,8 +88,8 @@ static int add_fixed_resources(struct device *dev, int index)
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); + printk(BIOS_DEBUG, "Adding PCIe config bar base = 0x%08x " + "size = 0x%x\n", pcie_config_base, pcie_config_size); resource = new_resource(dev, index++); resource->base = (resource_t) pcie_config_base; resource->size = (resource_t) pcie_config_size; diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c index e599e00..5aca229 100644 --- a/src/northbridge/intel/fsp_rangeley/udelay.c +++ b/src/northbridge/intel/fsp_rangeley/udelay.c @@ -19,7 +19,7 @@ #include <cpu/x86/msr.h>
/** - * Intel Rangeley CPUs always run the TSC at BCLK=100MHz + * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz */
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c index 4da5157..499d96f 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi.c +++ b/src/northbridge/intel/fsp_sandybridge/acpi.c @@ -41,7 +41,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) if (!dev) return current;
- pciexbar_reg=pci_read_config32(dev, PCIEXBAR); + pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
// MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl index 90d1b1a..dfe5e25 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl @@ -134,7 +134,7 @@ Device (MCHC) }
/* - * Search CPU0 _PSS looking for control=arg0 and then + * Search CPU0 _PSS looking for control = arg0 and then * return previous P-state entry number for new _PPC * * Format of _PSS: diff --git a/src/northbridge/intel/fsp_sandybridge/chip.h b/src/northbridge/intel/fsp_sandybridge/chip.h index eb86b83..bec2d9b 100644 --- a/src/northbridge/intel/fsp_sandybridge/chip.h +++ b/src/northbridge/intel/fsp_sandybridge/chip.h @@ -30,7 +30,7 @@ struct northbridge_intel_fsp_sandybridge_config { u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
- u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ + u8 gpu_panel_port_select; /* 0 = LVDS 1 = DP_B 2 = DP_C 3 = DP_D */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */ diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index 08c3b0c..888da8e 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -95,7 +95,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { - *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; if (Status == 0xFFFFFFFF) { hard_reset(); } diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c index a33cafa..cda9e08 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.c +++ b/src/northbridge/intel/fsp_sandybridge/gma.c @@ -31,7 +31,7 @@
u32 map_oprom_vendev(u32 vendev) { - u32 new_vendev=vendev; + u32 new_vendev = vendev;
switch (vendev) { case 0x80860102: /* GT1 Desktop */ @@ -41,7 +41,7 @@ u32 map_oprom_vendev(u32 vendev) case 0x80860122: /* GT2 Desktop >=1.3GHz */ case 0x80860126: /* GT2 Mobile >=1.3GHz */ case 0x80860166: /* IVB */ - new_vendev=0x80860106; /* GT1 Mobile */ + new_vendev = 0x80860106; /* GT1 Mobile */ break; }
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index 99d8fbb..42341d1 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -105,8 +105,8 @@ static void add_fixed_resources(struct device *dev, int index) mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); + printk(BIOS_DEBUG, "Adding PCIe config bar base = 0x%08x " + "size = 0x%x\n", pcie_config_base, pcie_config_size); resource = new_resource(dev, index++); resource->base = (resource_t) pcie_config_base; resource->size = (resource_t) pcie_config_size; diff --git a/src/northbridge/intel/fsp_sandybridge/udelay.c b/src/northbridge/intel/fsp_sandybridge/udelay.c index d482199..8f95595 100644 --- a/src/northbridge/intel/fsp_sandybridge/udelay.c +++ b/src/northbridge/intel/fsp_sandybridge/udelay.c @@ -19,7 +19,7 @@ #include <cpu/x86/msr.h>
/** - * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz + * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK = 100MHz */
void udelay(u32 us) diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index ce75aea..5ae0dbc 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -153,14 +153,14 @@ static void mch_domain_read_resources(device_t dev) (touud >> 10) - 4096); }
- printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " - "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10); + printk(BIOS_DEBUG, "Adding UMA memory area base = 0x%llx " + "size = 0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10); /* Don't use uma_resource() as our UMA touches the PCI hole. */ fixed_mem_resource(dev, 6, tomk, uma_sizek, IORESOURCE_RESERVE);
if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); + printk(BIOS_DEBUG, "Adding PCIe config bar base = 0x%08x " + "size = 0x%x\n", pcie_config_base, pcie_config_size); fixed_mem_resource(dev, 7, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } @@ -226,15 +226,15 @@ static void enable_dev(device_t dev) switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; + acpi_slp_type = 0; break; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; + acpi_slp_type = 3; break; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; + acpi_slp_type = 0; break; } #endif diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index f16be2c..3710104 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -39,7 +39,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) if (!dev) return current;
- pciexbar_reg=pci_read_config32(dev, PCIEXBAR); + pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
// MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index e3c7d11..2565851 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -144,7 +144,7 @@ Device (MCHC) }
/* - * Search CPU0 _PSS looking for control=arg0 and then + * Search CPU0 _PSS looking for control = arg0 and then * return previous P-state entry number for new _PPC * * Format of _PSS: diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 098bc33..3cf7a9e 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -30,7 +30,7 @@ struct northbridge_intel_haswell_config { u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
- u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ + u8 gpu_panel_port_select; /* 0 = LVDS 1 = DP_B 2 = DP_C 3 = DP_D */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index ea0bc54..1c7aff9 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -98,7 +98,7 @@ static const struct gt_reg haswell_gt_lock[] = {
u32 map_oprom_vendev(u32 vendev) { - u32 new_vendev=vendev; + u32 new_vendev = vendev;
switch (vendev) { case 0x80860402: /* GT1 Desktop */ @@ -116,7 +116,7 @@ u32 map_oprom_vendev(u32 vendev) case 0x8086042a: /* GT3 Server */ case 0x80860a26: /* GT3 ULT */
- new_vendev=0x80860406; /* GT1 Mobile */ + new_vendev = 0x80860406; /* GT1 Mobile */ break; }
diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c index 71a2bf2..3f4939c 100644 --- a/src/northbridge/intel/i3100/pciexp_porta.c +++ b/src/northbridge/intel/i3100/pciexp_porta.c @@ -54,7 +54,7 @@ static void pcie_scan_bridge(struct device *dev) pci_write_config16(dev, 0x74, (ctl | (1<<5))); val = pci_read_config16(dev, 0x76); printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); - flag=1; + flag = 1; hard_reset(); } } while (val & (3<<10)); diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index b5e35d6..62f485d 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -76,7 +76,7 @@ static void pcie_scan_bridge(struct device *dev) pci_write_config16(dev, 0x74, (ctl | (1<<5))); val = pci_read_config16(dev, 0x76); printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); - flag=1; + flag = 1; hard_reset(); } } while (val & (3<<10)); diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 39e40e0..1d21f46 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -235,7 +235,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, int cnt;
dra = 0; - for (cnt=0; cnt < 4; cnt++) { + for (cnt = 0; cnt < 4; cnt++) { if (!(dimm_mask & (1 << cnt))) { continue; } @@ -293,7 +293,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, u32 drt; int cnt; int first_dimm; - int cas_latency=0; + int cas_latency = 0; int latency; u32 index = 0; u32 index2 = 0; @@ -313,7 +313,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
drt |= (3<<18); /* Trasmax */
- for (cnt=0; cnt < 4; cnt++) { + for (cnt = 0; cnt < 4; cnt++) { if (!(dimm_mask & (1 << cnt))) { continue; } @@ -343,7 +343,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, else if ((index)==1) cas_latency = 25; else cas_latency = 30;
- for (cnt=0;cnt<4;cnt++) { + for (cnt = 0;cnt < 4;cnt++) { if (!(dimm_mask & (1 << cnt))) { continue; } @@ -549,7 +549,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
/* 0x7c DRC */ drc = pci_read_config32(ctrl->f0, DRC); - for (cnt=0; cnt < 4; cnt++) { + for (cnt = 0; cnt < 4; cnt++) { if (!(dimm_mask & (1 << cnt))) { continue; } @@ -616,8 +616,8 @@ static void do_delay(void) { int i; u8 b; - for (i=0;i<16;i++) - b=inb(0x80); + for (i = 0; i < 16; i++) + b = inb(0x80); }
#define TIMEOUT_LOOPS 300000 @@ -637,7 +637,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) /* ODT enable */ pci_write_config32(ctrl->f0, SDRC, 0x30000000); /* Figure out which slots are Empty, Single, or Double sided */ - for (i=0,t4=0,c2=0;i<8;i+=2) { + for (i = 0,t4 = 0,c2 = 0; i < 8; i+=2) { c1 = pci_read_config8(ctrl->f0, DRB+i); if (c1 == c2) continue; c2 = pci_read_config8(ctrl->f0, DRB+1+i); @@ -646,7 +646,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) else t4 |= (2 << (i*4)); } - for (i=0;i<1;i++) { + for (i = 0; i < 1; i++) { if ((t4&0x0f) == 1) { if ( ((t4>>8)&0x0f) == 0 ) { data32 = 0x00000010; /* EEES */ @@ -686,12 +686,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
- for (dimm=0;dimm<8;dimm+=2) { + for (dimm = 0;dimm < 8;dimm+=2) {
write32(MCBAR+DCALADDR, 0x0b840001); write32(MCBAR+DCALCSR, 0x81000003 | (dimm << 20));
- for (i=0;i<1001;i++) { + for (i = 0; i < 1001; i++) { data32 = read32(MCBAR+DCALCSR); if (!(data32 & (1<<31))) break; @@ -702,8 +702,8 @@ static void set_receive_enable(const struct mem_controller *ctrl) { u32 i; u32 cnt; - u32 recena=0; - u32 recenb=0; + u32 recena = 0; + u32 recenb = 0;
{ u32 dimm; @@ -717,18 +717,18 @@ static void set_receive_enable(const struct mem_controller *ctrl) u32 work32h; u32 data32r; int32_t recen; - for (dimm=0;dimm<8;dimm+=1) { + for (dimm = 0;dimm < 8;dimm+=1) {
if (!(dimm&1)) { write32(MCBAR+DCALDATA+(17*4), 0x04020000); write32(MCBAR+DCALCSR, 0x81800004 | (dimm << 20));
- for (i=0;i<1001;i++) { + for (i = 0; i < 1001; i++) { data32 = read32(MCBAR+DCALCSR); if (!(data32 & (1<<31))) break; } - if (i>=1000) + if (i >= 1000) continue;
dcal_data32_0 = read32(MCBAR+DCALDATA + 0); @@ -749,9 +749,9 @@ static void set_receive_enable(const struct mem_controller *ctrl) /* Calculate the timing value */ { u32 bit; - for (i=0,edge=0,bit=63,cnt=31,data32r=0, - work32l=dcal_data32_1,work32h=dcal_data32_3; - (i<4) && bit; i++) { + for (i = 0,edge = 0,bit = 63,cnt = 31,data32r = 0, + work32l = dcal_data32_1,work32h = dcal_data32_3; + (i < 4) && bit; i++) { for (;;bit--,cnt--) { if (work32l & (1<<cnt)) break; @@ -806,7 +806,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) recen = data32r; recen += 3; recen = recen>>2; - for (cnt=5;cnt<24;) { + for (cnt = 5;cnt < 24;) { for (;;cnt++) if (!(work32l & (1<<cnt))) break; @@ -851,7 +851,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) } } /* Check for Eratta problem */ - for (i=cnt=0;i<32;i+=8) { + for (i = cnt = 0; i < 32; i+=8) { if (((recena>>i)&0x0f)>7) { cnt+= 0x101; } @@ -864,7 +864,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) if (cnt&0x0f00) { cnt = (cnt&0x0f) - (cnt>>16); if (cnt>1) { - for (i=0;i<32;i+=8) { + for (i = 0; i < 32; i+=8) { if (((recena>>i)&0x0f)>7) { recena &= ~(0x0f<<i); recena |= (7<<i); @@ -872,7 +872,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) } } else { - for (i=0;i<32;i+=8) { + for (i = 0; i < 32; i+=8) { if (((recena>>i)&0x0f)<8) { recena &= ~(0x0f<<i); recena |= (8<<i); @@ -880,7 +880,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) } } } - for (i=cnt=0;i<32;i+=8) { + for (i = cnt = 0; i < 32; i+=8) { if (((recenb>>i)&0x0f)>7) { cnt+= 0x101; } @@ -893,7 +893,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) if (cnt & 0x0f00) { cnt = (cnt&0x0f) - (cnt>>16); if (cnt>1) { - for (i=0;i<32;i+=8) { + for (i = 0; i < 32; i+=8) { if (((recenb>>i)&0x0f)>7) { recenb &= ~(0x0f<<i); recenb |= (7<<i); @@ -901,7 +901,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) } } else { - for (i=0;i<32;i+=8) { + for (i = 0; i < 32; i+=8) { if (((recenb>>8)&0x0f)<8) { recenb &= ~(0x0f<<i); recenb |= (8<<i); @@ -986,7 +986,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 = data32 | (1 << 5); /* temp turn off ODT */ /* Set gearing, then dram controller mode */ /* drc bits 3:2 = FSB speed */ - for (iptr = gearing[(drc>>2)&3].clkgr,cnt=0;cnt<4;cnt++) { + for (iptr = gearing[(drc>>2)&3].clkgr,cnt = 0;cnt < 4;cnt++) { pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]); } /* 0x7c DRC */ @@ -1011,7 +1011,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* program DRT timing values */ cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
- for (i=0;i<8;i+=2) { /* loop through each dimm to test */ + for (i = 0; i < 8; i+=2) { /* loop through each dimm to test */ printk(BIOS_DEBUG, "DIMM %08x\n", i); /* Apply NOP */ do_delay(); @@ -1026,7 +1026,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Apply NOP */ do_delay();
- for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); @@ -1034,7 +1034,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Precharg all banks */ do_delay(); - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALADDR, 0x04000000); write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); do data32 = read32(MCBAR+DCALCSR); @@ -1043,7 +1043,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* EMRS dll's enabled */ do_delay(); - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { /* fixme hard code AL additive latency */ write32(MCBAR+DCALADDR, 0x0b940001); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); @@ -1056,7 +1056,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) mode_reg = 0x053a0000; else mode_reg = 0x054a0000; - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALADDR, mode_reg); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); do data32 = read32(MCBAR+DCALCSR); @@ -1067,7 +1067,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) do_delay(); do_delay(); do_delay(); - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALADDR, 0x04000000); write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); do data32 = read32(MCBAR+DCALCSR); @@ -1076,46 +1076,46 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Do 2 refreshes */ do_delay(); - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); } do_delay(); - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); } do_delay(); /* for good luck do 6 more */ - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); } do_delay(); - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); } do_delay(); - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); } do_delay(); - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); } do_delay(); - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); } do_delay(); - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); } do_delay(); /* MRS reset dll's normal */ do_delay(); - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24))); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); do data32 = read32(MCBAR+DCALCSR); @@ -1124,7 +1124,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Do only if DDR2 EMRS dll's enabled */ do_delay(); - for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALADDR, (0x0b940001)); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); do data32 = read32(MCBAR+DCALCSR); @@ -1156,11 +1156,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* clear memory and init ECC */ printk(BIOS_DEBUG, "Clearing memory\n"); - for (i=0;i<64;i+=4) { + for (i = 0; i < 64; i+=4) { write32(MCBAR+DCALDATA+i, 0x00000000); }
- for (cs=0;cs<8;cs+=2) { + for (cs = 0;cs < 8;cs+=2) { write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 001ec0d..fa557da 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -240,7 +240,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, /* set device type (registered) */ dra |= (1 << 14);
- /* set number of ranks (0=single, 1=dual) */ + /* set number of ranks (0 = single, 1 = dual) */ value = spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS); dra |= ((value & 0x1) << 17);
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 66282aa..de08970 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -516,7 +516,7 @@ static void set_dram_buffer_strength(void) * | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5# * | | | | | | | | | | ||||||| +----------- DQMA1/CASA1# * | | | | | | | | | | ||||||+------------- DQMA5/CASA5# - * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# [ 0=1x;1=2x ] + * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# [ 0 = 1x;1 = 2x ] * | | | | | | | | | +--------------------- CSA6#/CKE2# * | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4# * | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3# diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h index 0c55443..03ba8d8 100644 --- a/src/northbridge/intel/i5000/raminit.h +++ b/src/northbridge/intel/i5000/raminit.h @@ -284,14 +284,14 @@ struct i5000_fbd_branch { };
enum odt { - ODT_150OHM=1, - ODT_50OHM=4, - ODT_75OHM=2, + ODT_150OHM = 1, + ODT_50OHM = 4, + ODT_75OHM = 2, };
enum bl { - BL_BL4=1, - BL_BL8=2, + BL_BL4 = 1, + BL_BL8 = 2, };
struct i5000_fbd_setup { diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c index 667f874..cb35141 100644 --- a/src/northbridge/intel/i82830/smihandler.c +++ b/src/northbridge/intel/i82830/smihandler.c @@ -159,9 +159,9 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) printk(BIOS_DEBUG, "|- MBI_QueryInterface\n"); version = (version_t *)banner_id; version->banner.retsts = MSH_OK; - version->versionmajor=1; - version->versionminor=3; - version->smicombuffersize=0x1000; + version->versionmajor = 1; + version->versionminor = 3; + version->smicombuffersize = 0x1000; break; } case 0x0002: @@ -178,10 +178,10 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) printk(BIOS_DEBUG, "|- MBI_GetObjectHeader\n"); printk(BIOS_DEBUG, "| |- objnum = %d\n", obj_header->objnum);
- int i, count=0; + int i, count = 0; obj_header->banner.retsts = MSH_IF_NOT_FOUND;
- for (i=0; i<mbi_len;) { + for (i = 0; i < mbi_len;) { int len;
if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) { @@ -207,7 +207,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) obj_header->banner.retsts = MSH_OK; printk(BIOS_DEBUG, "| |- MBI module '"); int j; - for (j=0; j < mbi_header->name_len && mbi_header->name[j]; j++) + for (j = 0; j < mbi_header->name_len && mbi_header->name[j]; j++) printk(BIOS_DEBUG, "%c", mbi_header->name[j]); printk(BIOS_DEBUG, "' found.\n"); #ifdef DEBUG_SMI_I82830 @@ -235,10 +235,10 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) printk(BIOS_DEBUG, "| |- buflen = %x\n", getobj->buflen); printk(BIOS_DEBUG, "| |- buffer = %x\n", getobj->buffer);
- int i, count=0; + int i, count = 0; getobj->banner.retsts = MSH_IF_NOT_FOUND;
- for (i=0; i< mbi_len;) { + for (i = 0; i< mbi_len;) { int headerlen, objectlen;
if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) { diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 72a152c..71694c8 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -38,7 +38,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) if (!dev) return current;
- pciexbar_reg=pci_read_config32(dev, PCIEXBAR); + pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
// MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 946c984..fa00df8 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -105,7 +105,7 @@ void dump_mem(unsigned start, unsigned end) { unsigned i; printk(BIOS_DEBUG, "dump_mem:"); - for (i=start;i<end;i++) { + for (i = start; i < end; i++) { if ((i & 0xf)==0) { printk(BIOS_DEBUG, "\n%08x:", i); } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index f4d0916..dda41bd 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -752,7 +752,7 @@ static void i945_setup_pci_express_x16(void) };
int i; - for (i=0; i<ARRAY_SIZE(reglist); i++) { + for (i = 0; i < ARRAY_SIZE(reglist); i++) { reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]); reg32 &= 0x0fffffff; reg32 |= (2 << 28); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 02caa0a..9d81171 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -121,7 +121,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
for (i = 0; i < 2; i++) for (j = 0; j < 0x100; j++) - /* R=j, G=j, B=j. */ + /* R = j, G = j, B = j. */ write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j);
write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -423,7 +423,7 @@ static void gma_func0_init(struct device *dev) mmiobase = (void *)(uintptr_t)dev->resource_list[0].base; graphics_base = dev->resource_list[2].base;
- printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", + printk(BIOS_SPEW, "GMADR = 0x%08x GTTADR = 0x%08x\n", pci_read_config32(dev, GMADR), pci_read_config32(dev, GTTADR) ); diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 719a795..ba8b251 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -224,15 +224,15 @@ static void northbridge_init(struct device *dev) switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; + acpi_slp_type = 0; break; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; + acpi_slp_type = 3; break; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; + acpi_slp_type = 0; break; } } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 8c674e9..bd80e4e 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -96,7 +96,7 @@ void sdram_dump_mchbar_registers(void) int i; printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
- for (i=0; i<0xfff; i+=4) { + for (i = 0; i < 0xfff; i+=4) { if (MCHBAR32(i) == 0) continue; printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i)); @@ -359,7 +359,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) * */
- for (i=0; i<(2 * DIMM_SOCKETS); i++) { + for (i = 0; i<(2 * DIMM_SOCKETS); i++) { int device = get_dimm_spd_address(sysinfo, i); u8 reg8;
@@ -443,7 +443,7 @@ static void sdram_verify_package_type(struct sys_info * sysinfo)
/* Assume no stacked DIMMs are available until we find one */ sysinfo->package = 0; - for (i=0; i<2*DIMM_SOCKETS; i++) { + for (i = 0; i < 2*DIMM_SOCKETS; i++) { if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue;
@@ -463,7 +463,7 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo) SPD_CAS_LATENCY_DDR2_4 | SPD_CAS_LATENCY_DDR2_5;
- for (i=0; i<2*DIMM_SOCKETS; i++) { + for (i = 0; i < 2*DIMM_SOCKETS; i++) { if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED) cas_mask &= spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_ACCEPTABLE_CAS_LATENCIES); @@ -515,11 +515,11 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 } PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas);
- for (j = max_ram_speed; j>=0; j--) { + for (j = max_ram_speed; j >= 0; j--) { int freq_cas_mask = cas_mask;
PRINTK_DEBUG("Probing Speed %d\n", j); - for (i=0; i<2*DIMM_SOCKETS; i++) { + for (i = 0; i < 2*DIMM_SOCKETS; i++) { int device = get_dimm_spd_address(sysinfo, i); int current_cas_mask;
@@ -616,7 +616,7 @@ static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo) tRAS_cycles = 4; /* 4 clocks minimum */ tRAS_time = tRAS_cycles * freq_multiplier;
- for (i=0; i<2*DIMM_SOCKETS; i++) { + for (i = 0; i < 2*DIMM_SOCKETS; i++) { u8 reg8;
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) @@ -656,7 +656,7 @@ static void sdram_detect_smallest_tRP(struct sys_info * sysinfo) tRP_cycles = 2; /* 2 clocks minimum */ tRP_time = tRP_cycles * freq_multiplier;
- for (i=0; i<2*DIMM_SOCKETS; i++) { + for (i = 0; i < 2*DIMM_SOCKETS; i++) { u8 reg8;
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) @@ -697,7 +697,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo) tRCD_cycles = 2; /* 2 clocks minimum */ tRCD_time = tRCD_cycles * freq_multiplier;
- for (i=0; i<2*DIMM_SOCKETS; i++) { + for (i = 0; i < 2*DIMM_SOCKETS; i++) { u8 reg8;
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) @@ -737,7 +737,7 @@ static void sdram_detect_smallest_tWR(struct sys_info * sysinfo) tWR_cycles = 2; /* 2 clocks minimum */ tWR_time = tWR_cycles * freq_multiplier;
- for (i=0; i<2*DIMM_SOCKETS; i++) { + for (i = 0; i < 2*DIMM_SOCKETS; i++) { u8 reg8;
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) @@ -772,7 +772,7 @@ static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo) 25, 35, 43 /* DDR2-667 */ };
- for (i=0; i<2*DIMM_SOCKETS; i++) { + for (i = 0; i < 2*DIMM_SOCKETS; i++) { u8 reg8;
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) @@ -818,7 +818,7 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
sysinfo->refresh = 0;
- for (i=0; i<2*DIMM_SOCKETS; i++) { + for (i = 0; i < 2*DIMM_SOCKETS; i++) { int refresh;
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) @@ -849,7 +849,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo) { int i;
- for (i=0; i<2*DIMM_SOCKETS; i++) { + for (i = 0; i < 2*DIMM_SOCKETS; i++) { if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue;
@@ -861,7 +861,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo)
static void sdram_program_dram_width(struct sys_info * sysinfo) { - u16 c0dramw=0, c1dramw=0; + u16 c0dramw = 0, c1dramw = 0; int idx;
if (sysinfo->dual_channel) @@ -899,7 +899,7 @@ static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table) { int i;
- for (i=0; i<16; i++) + for (i = 0; i < 16; i++) MCHBAR32(offset+(i*4)) = slew_rate_table[i]; }
@@ -1242,12 +1242,12 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo)
/* We drive both channels with the same speed */ switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */ - case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */ - case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */ + case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */ + case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */ + case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */ }
- for (i=0; i < 4; i++) { + for (i = 0; i < 4; i++) { MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll; MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll; @@ -1559,10 +1559,10 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) static int sdram_set_row_attributes(struct sys_info *sysinfo) { int i, value; - u16 dra0=0, dra1=0, dra = 0; + u16 dra0 = 0, dra1 = 0, dra = 0;
printk(BIOS_DEBUG, "Setting row attributes...\n"); - for (i=0; i < 2 * DIMM_SOCKETS; i++) { + for (i = 0; i < 2 * DIMM_SOCKETS; i++) { u16 device; u8 columnsrows;
@@ -1616,7 +1616,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo) MCHBAR16(C0BNKARC) &= 0xff00;
off32 = C0BNKARC; - for (i=0; i < 2 * DIMM_SOCKETS; i++) { + for (i = 0; i < 2 * DIMM_SOCKETS; i++) { /* Switch to second channel */ if (i == DIMM_SOCKETS) off32 = C1BNKARC; @@ -1662,7 +1662,7 @@ static void sdram_program_cke_tristate(struct sys_info *sysinfo)
reg32 = MCHBAR32(C0DRC1);
- for (i=0; i < 4; i++) { + for (i = 0; i < 4; i++) { if (sysinfo->banksize[i] == 0) { reg32 |= (1 << (16 + i)); } @@ -1676,7 +1676,7 @@ static void sdram_program_cke_tristate(struct sys_info *sysinfo) /* Do we have to do this if we're in Single Channel Mode? */ reg32 = MCHBAR32(C1DRC1);
- for (i=4; i < 8; i++) { + for (i = 4; i < 8; i++) { if (sysinfo->banksize[i] == 0) { reg32 |= (1 << (12 + i)); } @@ -1695,7 +1695,7 @@ static void sdram_program_odt_tristate(struct sys_info *sysinfo)
reg32 = MCHBAR32(C0DRC2);
- for (i=0; i < 4; i++) { + for (i = 0; i < 4; i++) { if (sysinfo->banksize[i] == 0) { reg32 |= (1 << (24 + i)); } @@ -1704,7 +1704,7 @@ static void sdram_program_odt_tristate(struct sys_info *sysinfo)
reg32 = MCHBAR32(C1DRC2);
- for (i=4; i < 8; i++) { + for (i = 4; i < 8; i++) { if (sysinfo->banksize[i] == 0) { reg32 |= (1 << (20 + i)); } @@ -1832,7 +1832,7 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo) /* Determine page size */ reg32 = 0; page_size = 1; /* Default: 1k pagesize */ - for (i=0; i< 2*DIMM_SOCKETS; i++) { + for (i = 0; i< 2*DIMM_SOCKETS; i++) { if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS) page_size = 2; /* 2k pagesize */ @@ -1932,7 +1932,7 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo)
MCHBAR32(DCC) = reg32;
- PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC)); + PRINTK_DEBUG("DCC = 0x%08x\n", MCHBAR32(DCC)); }
static void sdram_program_pll_settings(struct sys_info *sysinfo) @@ -1980,7 +1980,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) voltage = VOLTAGE_1_05; if (MCHBAR32(DFT_STRAP1) & (1 << 20)) voltage = VOLTAGE_1_50; - printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V"); + printk(BIOS_DEBUG, "Voltage: %s ", (voltage == VOLTAGE_1_05)?"1.05V":"1.5V");
/* Gate graphics hardware for frequency change */ reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1); @@ -2006,7 +2006,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) if (freq != CRCLK_400MHz) { /* What chipset are we? Force 166MHz for GMS */ reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4; - if (reg8==2) + if (reg8 == 2) freq = CRCLK_166MHz; }
@@ -2043,9 +2043,9 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) }
if (second_vco) { - sysinfo->clkcfg_bit7=1; + sysinfo->clkcfg_bit7 = 1; } else { - sysinfo->clkcfg_bit7=0; + sysinfo->clkcfg_bit7 = 0; }
/* Graphics Core Render Clock */ @@ -2089,7 +2089,7 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
clkcfg = MCHBAR32(CLKCFG);
- printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg); + printk(BIOS_DEBUG, "CLKCFG = 0x%08x, ", clkcfg);
clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
@@ -2153,7 +2153,7 @@ cache_code: goto vco_update; out:
- printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG)); + printk(BIOS_DEBUG, "CLKCFG = 0x%08x, ", MCHBAR32(CLKCFG)); printk(BIOS_DEBUG, "ok\n"); }
@@ -2504,7 +2504,7 @@ static void sdram_power_management(struct sys_info *sysinfo)
MCHBAR32(UPMC3) = 0x000f06ff;
- for (i=0; i<5; i++) { + for (i = 0; i < 5; i++) { MCHBAR32(UPMC3) &= ~(1 << 16); MCHBAR32(UPMC3) |= (1 << 16); } @@ -2685,7 +2685,7 @@ static void sdram_save_receive_enable(void) * so we grab bytes 128 - 131 to save the receive enable values */
- for (i=0; i<4; i++) + for (i = 0; i < 4; i++) cmos_write(values[i], 128 + i); }
@@ -2695,7 +2695,7 @@ static void sdram_recover_receive_enable(void) u32 reg32; u8 values[4];
- for (i=0; i<4; i++) + for (i = 0; i < 4; i++) values[i] = cmos_read(128 + i);
MCHBAR8(C0WL0REOST) = values[0]; diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index f4d9315..23f5dc4 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -63,7 +63,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse) { u32 reg32;
- printk(BIOS_SPEW, " set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse); + printk(BIOS_SPEW, " set_receive_enable() medium = 0x%x, coarse = 0x%x\n", medium, coarse);
reg32 = MCHBAR32(C0DRT1 + channel_offset); reg32 &= 0xf0ffffff; diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index 337a9bc..d5e17b2 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -96,7 +96,7 @@ Device (MCHC) }
/* - * Search CPU0 _PSS looking for control=arg0 and then + * Search CPU0 _PSS looking for control = arg0 and then * return previous P-state entry number for new _PPC * * Format of _PSS: diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index a9d136b..14eda0f 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -30,7 +30,7 @@ struct northbridge_intel_nehalem_config { u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
- u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ + u8 gpu_panel_port_select; /* 0 = LVDS 1 = DP_B 2 = DP_C 3 = DP_D */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */ diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 3b73929..b4ae20f 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -388,7 +388,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) /* 6: ECO bits */ reg32 = gtt_read(0xa180); reg32 |= (1 << 26) | (1 << 31); - /* (bit 20=1 for SNB step D1+ / IVB A0+) */ + /* (bit 20 = 1 for SNB step D1+ / IVB A0+) */ if (bridge_silicon_revision() >= SNB_STEP_D1) reg32 |= (1 << 20); gtt_write(0xa180, reg32); diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index bf35731..d345d20 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -120,8 +120,8 @@ static void mch_domain_read_resources(device_t dev) }
if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); + printk(BIOS_DEBUG, "Adding PCIe config bar base = 0x%08x " + "size = 0x%x\n", pcie_config_base, pcie_config_size); fixed_mem_resource(dev, index++, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 4953144..b819ca6 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -43,7 +43,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) if (!dev) return current;
- pciexbar_reg=pci_read_config32(dev, PCIEXBAR); + pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
// MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 5988489..ceb68cb 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -134,7 +134,7 @@ Device (MCHC) }
/* - * Search CPU0 _PSS looking for control=arg0 and then + * Search CPU0 _PSS looking for control = arg0 and then * return previous P-state entry number for new _PPC * * Format of _PSS: diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index d002824..6339045 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -30,7 +30,7 @@ struct northbridge_intel_sandybridge_config { u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
- u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ + u8 gpu_panel_port_select; /* 0 = LVDS 1 = DP_B 2 = DP_C 3 = DP_D */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */ diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index bd0de4a..2e0c05a 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -254,7 +254,7 @@ static const struct gt_powermeter ivb_pm_gt2_35w[] = {
u32 map_oprom_vendev(u32 vendev) { - u32 new_vendev=vendev; + u32 new_vendev = vendev;
switch (vendev) { case 0x80860102: /* GT1 Desktop */ @@ -265,7 +265,7 @@ u32 map_oprom_vendev(u32 vendev) case 0x80860126: /* GT2 Mobile >=1.3GHz */ case 0x80860156: /* IVB */ case 0x80860166: /* IVB */ - new_vendev=0x80860106; /* GT1 Mobile */ + new_vendev = 0x80860106; /* GT1 Mobile */ break; }
@@ -394,7 +394,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) /* 6: ECO bits */ reg32 = gtt_read(0xa180); reg32 |= (1 << 26) | (1 << 31); - /* (bit 20=1 for SNB step D1+ / IVB A0+) */ + /* (bit 20 = 1 for SNB step D1+ / IVB A0+) */ if (bridge_silicon_revision() >= SNB_STEP_D1) reg32 |= (1 << 20); gtt_write(0xa180, reg32); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 53d93a2..1da401f 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -104,8 +104,8 @@ static void add_fixed_resources(struct device *dev, int index) mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); + printk(BIOS_DEBUG, "Adding PCIe config bar base = 0x%08x " + "size = 0x%x\n", pcie_config_base, pcie_config_size); resource = new_resource(dev, index++); resource->base = (resource_t) pcie_config_base; resource->size = (resource_t) pcie_config_size; @@ -476,15 +476,15 @@ static void northbridge_enable(device_t dev) switch (pci_read_config32(dev, SKPAD)) { case 0xcafebabe: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; + acpi_slp_type = 0; break; case 0xcafed00d: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; + acpi_slp_type = 3; break; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; + acpi_slp_type = 0; break; } #endif diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index 7362f75..9fc54cd 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -19,7 +19,7 @@ #include <cpu/x86/msr.h>
/** - * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz + * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK = 100MHz */
void udelay(u32 us) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 15e150e..9c268bc 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -95,8 +95,8 @@ static void mch_domain_read_resources(device_t dev) (touud - top32memk) >> 10); }
- printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x " - "size=0x%08x\n", usable_tomk << 10, uma_sizek << 10); + printk(BIOS_DEBUG, "Adding UMA memory area base = 0x%08x " + "size = 0x%08x\n", usable_tomk << 10, uma_sizek << 10); fixed_mem_resource(dev, index++, usable_tomk, uma_sizek, IORESOURCE_RESERVE);
@@ -106,8 +106,8 @@ static void mch_domain_read_resources(device_t dev) IORESOURCE_RESERVE);
if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); + printk(BIOS_DEBUG, "Adding PCIe config bar base = 0x%08x " + "size = 0x%x\n", pcie_config_base, pcie_config_size); fixed_mem_resource(dev, index++, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index cd5b3b2..e96ec19 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -1239,7 +1239,7 @@ static void rcven_ddr2(struct sysinfo *s) addr += 128*1024*1024; } for (lane = 0; lane < 8; lane++) { - printk(BIOS_DEBUG, "Channel %d, Lane %d addr=0x%08x\n", ch, lane, addr); + printk(BIOS_DEBUG, "Channel %d, Lane %d addr = 0x%08x\n", ch, lane, addr); coarsecommon = (s->selected_timings.CAS - 1); switch (lane) { case 0: case 1: medium = 0; break; diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index f85f68e..e4384ce 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -258,9 +258,9 @@ static void sdram_set_registers(const struct mem_controller *ctrl) { u8 reg;
- /* Set WR=5 */ + /* Set WR = 5 */ pci_write_config8(ctrl->d0f3, 0x61, 0xe0); - /* Set CAS=4 */ + /* Set CAS = 4 */ pci_write_config8(ctrl->d0f3, 0x62, 0xfa); /* DRAM timing-3 */ pci_write_config8(ctrl->d0f3, 0x63, 0xca); @@ -283,7 +283,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) pci_write_config8(ctrl->d0f3, 0x52, 0x33); pci_write_config8(ctrl->d0f3, 0x53, 0x3f);
- /* Set to DDR2 SDRAM, BL=8 (0xc8, 0xc0 for bl=4) */ + /* Set to DDR2 SDRAM, BL = 8 (0xc8, 0xc0 for bl = 4) */ pci_write_config8(ctrl->d0f3, 0x6c, 0xc8);
/* DRAM Bus Turn-Around Setting */ @@ -426,7 +426,7 @@ static void sdram_enable(device_t dev, u8 *rank_address)
/* 6. Mode register set. */ PRINT_DEBUG_MEM("RAM Enable 6: Mode register set\n"); - /* Safe value for now, BL=8, WR=5, CAS=4 */ + /* Safe value for now, BL = 8, WR = 5, CAS = 4 */ /* * (E)MRS values are from the BPG. No direct explanation is given, but * they should somehow conform to the JEDEC DDR2 SDRAM Specification diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 10b7f65..4925f2b 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -35,16 +35,16 @@
static int via_cn700_int15_handler(void) { - int res=0; + int res = 0; printk(BIOS_DEBUG, "via_cn700_int15_handler\n"); switch(X86_EAX & 0xffff) { case 0x5f19: break; case 0x5f18: - X86_EAX=0x5f; - X86_EBX=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory - X86_ECX=0x060; - res=1; + X86_EAX = 0x5f; + X86_EBX = 0x545; // MCLK = 133, 32M frame buffer, 256 M main memory + X86_ECX = 0x060; + res = 1; break; case 0x5f00: X86_EAX = 0x8600; @@ -55,14 +55,14 @@ static int via_cn700_int15_handler(void) res = 1; break; case 0x5f02: - X86_EAX=0x5f; - X86_EBX= (X86_EBX & 0xffff0000) | 2; - X86_ECX= (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only - X86_EDX= (X86_EDX & 0xffff0000) | 0; // TV Layout - default - res=1; + X86_EAX = 0x5f; + X86_EBX = (X86_EBX & 0xffff0000) | 2; + X86_ECX = (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only + X86_EDX = (X86_EDX & 0xffff0000) | 0; // TV Layout - default + res = 1; break; case 0x5f0f: - X86_EAX=0x860f; + X86_EAX = 0x860f; break; default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", diff --git a/src/northbridge/via/cx700/agp.c b/src/northbridge/via/cx700/agp.c index 927fa21..deada76 100644 --- a/src/northbridge/via/cx700/agp.c +++ b/src/northbridge/via/cx700/agp.c @@ -38,7 +38,7 @@ static void agp_bridge_init(device_t dev)
/* * Since Internal Graphic already set to AGP3.0 compatible in its Capability Pointer - * We must set RAGP8X=1 B0D0F0 Rx84[3]=1 from backdoor register B0D0F0 RxB5[1:0]=11b + * We must set RAGP8X = 1 B0D0F0 Rx84[3]=1 from backdoor register B0D0F0 RxB5[1:0]=11b */ north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x0324, 0); reg8 = pci_read_config8(north_dev, 0xb5); diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c index 6109ea0..44aa743 100644 --- a/src/northbridge/via/cx700/early_smbus.c +++ b/src/northbridge/via/cx700/early_smbus.c @@ -142,7 +142,7 @@ static void set_ics_data(unsigned char dev, int data, char len) outb(0xff, SMBBLKDAT); }
- //for (i=0; i < len; i++) + //for (i = 0; i < len; i++) // outb(data[i],SMBBLKDAT);
outb(dev, SMBXMITADD); diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 2d74316..e9e4d98 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -87,7 +87,7 @@ static void setup_pm(device_t dev) /* set ACPI irq to 9 */ pci_write_config8(dev, 0x82, 0x49);
- /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ + /* Primary interupt channel, define wake events 0 = IRQ0 15 = IRQ15 1 = en. */ pci_write_config16(dev, 0x84, 0x609a);
/* SMI output level to low, 7.5us throttle clock */ diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 7d3fcbe..5647ca0 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -90,7 +90,7 @@
#define REGISTERPRESET(bus,dev,fun,bdfspec) \ { u8 j, reg; \ - for (j=0; j<(sizeof((bdfspec))/sizeof(struct regmask)); j++) { \ + for (j = 0; j<(sizeof((bdfspec))/sizeof(struct regmask)); j++) { \ printk(BIOS_DEBUG, "Writing bus " #bus " dev " #dev " fun " #fun " register "); \ printk(BIOS_DEBUG, "%02x", (bdfspec)[j].reg); \ printk(BIOS_DEBUG, "\n"); \ @@ -303,8 +303,8 @@ static const u8 Init_Rank_Reg_Table[] = {
static const u16 DDR2_MRS_table[] = { /* CL: 2, 3, 4, 5 */ - 0x150, 0x1d0, 0x250, 0x2d0, /* BL=4 ;Use 1X-bandwidth MA table to init DRAM */ - 0x158, 0x1d8, 0x258, 0x2d8, /* BL=8 ;Use 1X-bandwidth MA table to init DRAM */ + 0x150, 0x1d0, 0x250, 0x2d0, /* BL = 4 ;Use 1X-bandwidth MA table to init DRAM */ + 0x158, 0x1d8, 0x258, 0x2d8, /* BL = 8 ;Use 1X-bandwidth MA table to init DRAM */ };
#define MRS_DDR2_TWR2 ((0 << 15) | (0 << 20) | (1 << 12)) @@ -1050,7 +1050,7 @@ static void step_2_19(const struct mem_controller *ctrl) /* Step 17. Mode register set. Wait 200us. */ printk(BIOS_SPEW, "\nRAM Enable 4: Mode register set\n");
- //safe value for now, BL=8, WR=4, CAS=4 + //safe value for now, BL = 8, WR = 4, CAS = 4 do_ram_command(ctrl, RAM_COMMAND_MRS); udelay(200);
diff --git a/src/northbridge/via/cx700/vga.c b/src/northbridge/via/cx700/vga.c index 16f0ea0..7cb84d2 100644 --- a/src/northbridge/via/cx700/vga.c +++ b/src/northbridge/via/cx700/vga.c @@ -42,7 +42,7 @@
static int via_cx700_int15_handler(void) { - int res=0; + int res = 0; u8 mem_speed;
#define MEMORY_SPEED_66MHZ (0 << 4) @@ -83,7 +83,7 @@ static int via_cx700_int15_handler(void) X86_ECX = 0x00000000; // 0 -> default // TV Layout - default X86_EDX = (X86_EDX & 0xffffff00) | 0; - res=1; + res = 1; break;
case 0x5f0b: /* Get Expansion Setting */ @@ -91,12 +91,12 @@ static int via_cx700_int15_handler(void)
X86_ECX = X86_ECX & 0xffffff00; // non-expansion // regs->ecx = regs->ecx & 0xffffff00 | 1; // expansion - res=1; + res = 1; break;
case 0x5f0f: /* VGA Post Completion */ X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f; - res=1; + res = 1; break;
case 0x5f18: @@ -113,7 +113,7 @@ static int via_cx700_int15_handler(void)
X86_EBX |= memory_mapping[mem_speed];
- res=1; + res = 1; break;
default: diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index 8196050..d37ad4f 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -38,13 +38,13 @@ static const u8 DramRegTbl[][3] = { /* Reg AND OR */ {0x50, 0x11, 0xEE}, // DDR default MA7 for DRAM init {0x51, 0x11, 0x60}, // DDR default MA3 for CHB init - {0x52, 0x00, 0x33}, // DDR use BA0=M17, BA1=M18, - {0x53, 0x00, 0x3F}, // DDR BA2=M19 + {0x52, 0x00, 0x33}, // DDR use BA0 = M17, BA1 = M18, + {0x53, 0x00, 0x3F}, // DDR BA2 = M19
- {0x54, 0x00, 0x00}, // default PR0=VR0; PR1=VR1 - {0x55, 0x00, 0x00}, // default PR2=VR2; PR3=VR3 - {0x56, 0x00, 0x00}, // default PR4=VR4; PR5=VR5 - {0x57, 0x00, 0x00}, // default PR4=VR4; PR5=VR5 + {0x54, 0x00, 0x00}, // default PR0 = VR0; PR1 = VR1 + {0x55, 0x00, 0x00}, // default PR2 = VR2; PR3 = VR3 + {0x56, 0x00, 0x00}, // default PR4 = VR4; PR5 = VR5 + {0x57, 0x00, 0x00}, // default PR4 = VR4; PR5 = VR5
{0x60, 0x00, 0x00}, // disable fast turn-around {0x65, 0x00, 0xD9}, // AGP timer = 0XD; Host timer = 8; @@ -317,15 +317,15 @@ Purpose : Initialize DDR2 by standard sequence ===================================================================*/
// DLL: Enable Reset -static const u32 CHA_MRS_DLL_150[2] = { 0x00020200, 0x00000800 }; // with 150 ohm (A17=1, A9=1), (A11=1)(cpu address) -static const u32 CHA_MRS_DLL_75[2] = { 0x00020020, 0x00000800 }; // with 75 ohm (A17=1, A5=1), (A11=1)(cpu address) +static const u32 CHA_MRS_DLL_150[2] = { 0x00020200, 0x00000800 }; // with 150 ohm (A17 = 1, A9 = 1), (A11 = 1)(cpu address) +static const u32 CHA_MRS_DLL_75[2] = { 0x00020020, 0x00000800 }; // with 75 ohm (A17 = 1, A5 = 1), (A11 = 1)(cpu address)
// CPU(DRAM) // { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 } // { DLL: reset. A11(MA8)=1 } // -// DDR2 CL=2 CL=3 CL=4 CL=5 CL=6(Burst type=interleave)(WR fine tune in code) -static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL=4 ;Use 1X-bandwidth MA table to init DRAM +// DDR2 CL = 2 CL = 3 CL = 4 CL = 5 CL = 6(Burst type = interleave)(WR fine tune in code) +static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL = 4 ;Use 1X-bandwidth MA table to init DRAM
// MA11 MA10(AP) MA9 #define CHA_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h @@ -334,20 +334,20 @@ static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 #define CHA_MRS_DDR2_TWR5 (1 << 13) + (0 << 20) + (0 << 12) // Value = 002000h #define CHA_MRS_DDR2_TWR6 (1 << 13) + (0 << 20) + (1 << 12) // Value = 003000h
-// DDR2 Twr=2 Twr=3 Twr=4 Twr=5 +// DDR2 Twr = 2 Twr = 3 Twr = 4 Twr = 5 static const u32 CHA_DDR2_Twr_table[5] = { CHA_MRS_DDR2_TWR2, CHA_MRS_DDR2_TWR3, CHA_MRS_DDR2_TWR4, CHA_MRS_DDR2_TWR5, CHA_MRS_DDR2_TWR6 };
-#define CHA_OCD_Exit_150ohm 0x20200 // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=1 ,A5=0 (CPU address) -#define CHA_OCD_Default_150ohm 0x21E00 // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=1 ,A5=0 (CPU address) -#define CHA_OCD_Exit_75ohm 0x20020 // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=0 ,A5=1 (CPU address) -#define CHA_OCD_Default_75ohm 0x21C20 // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=0 ,A5=1 (CPU address) +#define CHA_OCD_Exit_150ohm 0x20200 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 1,MA2 = 0 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 0,A9 = 1 ,A5 = 0 (CPU address) +#define CHA_OCD_Default_150ohm 0x21E00 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 1,MA2 = 0 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 1,A9 = 1 ,A5 = 0 (CPU address) +#define CHA_OCD_Exit_75ohm 0x20020 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 0,MA2 = 1 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 0,A9 = 0 ,A5 = 1 (CPU address) +#define CHA_OCD_Default_75ohm 0x21C20 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 0,MA2 = 1 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 1,A9 = 0 ,A5 = 1 (CPU address)
void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr) { @@ -527,14 +527,14 @@ Purpose : Initialize DDR2 of CHB by standard sequence Reference : ===================================================================*/ /*// DLL: Enable Reset -static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17=1, A9=1), (A11=1)(cpu address) -//u32 CHB_MRS_DLL_75[2] = { 0x00020020 | (1 << 20), 0x00000800 }; // with 75 ohm (A17=1, A5=1), (A11=1)(cpu address) +static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17 = 1, A9 = 1), (A11 = 1)(cpu address) +//u32 CHB_MRS_DLL_75[2] = { 0x00020020 | (1 << 20), 0x00000800 }; // with 75 ohm (A17 = 1, A5 = 1), (A11 = 1)(cpu address) // CPU(DRAM) // { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 } // { DLL: reset. A11(MA8)=1 } // -// DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) -static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL=4 ;Use 1X-bandwidth MA table to init DRAM +// DDR2 CL = 2 CL = 3 CL = 4 CL = 5 (Burst type = interleave)(WR fine tune in code) +static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL = 4 ;Use 1X-bandwidth MA table to init DRAM
// MA11 MA10(AP) MA9 #define CHB_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h @@ -543,17 +543,17 @@ static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // #define CHB_MRS_DDR2_TWR5 (1 << 13) + (0 << 20) + (0 << 12) // Value = 002000h #define CHB_MRS_DDR2_TWR6 (1 << 13) + (0 << 20) + (1 << 12) // Value = 003000h
-// DDR2 Twr=2 Twr=3 Twr=4 Twr=5 +// DDR2 Twr = 2 Twr = 3 Twr = 4 Twr = 5 static const u32 CHB_DDR2_Twr_table[5] = { CHB_MRS_DDR2_TWR2, CHB_MRS_DDR2_TWR3, CHB_MRS_DDR2_TWR4, CHB_MRS_DDR2_TWR5, CHB_MRS_DDR2_TWR6 };
-#define CHB_OCD_Exit_150ohm 0x20200 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=1 ,A5=0 (CPU address) -#define CHB_OCD_Default_150ohm 0x21E00 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=1 ,A5=0 (CPU address) -//#define CHB_OCD_Exit_75ohm 0x20020 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=0 ,A5=1 (CPU address) -//#define CHB_OCD_Default_75ohm 0x21C20 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=0 ,A5=1 (CPU address) +#define CHB_OCD_Exit_150ohm 0x20200 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 1,MA2 = 0 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 0,A9 = 1 ,A5 = 0 (CPU address) +#define CHB_OCD_Default_150ohm 0x21E00 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 1,MA2 = 0 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 1,A9 = 1 ,A5 = 0 (CPU address) +//#define CHB_OCD_Exit_75ohm 0x20020 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 0,MA2 = 1 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 0,A9 = 0 ,A5 = 1 (CPU address) +//#define CHB_OCD_Default_75ohm 0x21C20 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 0,MA2 = 1 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 1,A9 = 0 ,A5 = 1 (CPU address) void InitDDR2CHB( DRAM_SYS_ATTR *DramAttr ) @@ -568,27 +568,27 @@ void InitDDR2CHB(
// step3. //disable bank paging and multi page - Data=pci_read_config8(MEMCTRL, 0x69); + Data = pci_read_config8(MEMCTRL, 0x69); Data &= ~0x03; pci_write_config8(MEMCTRL, 0x69, Data);
- Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data);
//step 4. Initialize CHB begin - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data |= 0x40; pci_write_config8(MEMCTRL, 0xd3, Data);
//Step 5. NOP command enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd7, Data);
//Step 6. issue a nop cycle,RegD3[7] 0 -> 1 - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; @@ -603,25 +603,25 @@ void InitDDR2CHB(
// Step 8. // all banks precharge command enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x10; pci_write_config8(MEMCTRL, 0xd7, Data);
//step 9. issue a precharge all cycle,RegD3[7] 0 -> 1 - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data);
//step10. EMRS enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data);
- Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -634,25 +634,25 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xff00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data);
- Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data);
//step12. issue EMRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data);
//step13. MSR enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data);
- Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -665,13 +665,13 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xff00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data);
- Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data);
//step15. issue MRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; @@ -682,21 +682,21 @@ void InitDDR2CHB( pci_write_config8(MEMCTRL, 0xda, Data);
//step16. all banks precharge command enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x10; pci_write_config8(MEMCTRL, 0xd7, Data);
// step17. issue precharge all cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data);
//step18. CBR cycle enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x20; pci_write_config8(MEMCTRL, 0xd7, Data); @@ -706,7 +706,7 @@ void InitDDR2CHB( for (Idx = 0; Idx < 8; Idx++) { // issue CBR cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; @@ -716,12 +716,12 @@ void InitDDR2CHB( }
//step22. MSR enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data);
- Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -730,11 +730,11 @@ void InitDDR2CHB( //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.) //------------------------------------------------------------- //Burst Length : really offset Rx6c[1] - Data=pci_read_config8(MEMCTRL, 0x6C); + Data = pci_read_config8(MEMCTRL, 0x6C); BL = (Data & 0x02) >> 1;
// CL = really offset RX62[2:0] - Data=pci_read_config8(MEMCTRL, 0x62); + Data = pci_read_config8(MEMCTRL, 0x62); CL = Data & 0x03;
AccessAddr = (u32)(CHB_DDR2_MRS_table[CL]); @@ -744,7 +744,7 @@ void InitDDR2CHB( }
//Write recovery : really offset Rx63[7:5] - Data=pci_read_config8(MEMCTRL, 0x63); + Data = pci_read_config8(MEMCTRL, 0x63); Twr = (Data & 0xE0) >> 5;
AccessAddr += CHB_DDR2_Twr_table[Twr]; @@ -758,25 +758,25 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xFF00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data);
- Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)(((AccessAddr & 0x30000)>>16) << 1); pci_write_config8(MEMCTRL, 0xd7, Data);
//step 24. issue MRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data);
//step 25. EMRS enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data);
- Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -790,25 +790,25 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xff00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data);
- Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data);
//step 27. issue EMRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data);
//step 25. EMRS enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data);
- Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -821,13 +821,13 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xff00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data);
- Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data);
//step 29. issue EMRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; @@ -840,29 +840,29 @@ void InitDDR2CHB( Data = 0x00; pci_write_config8(MEMCTRL, 0xda, Data);
- Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; pci_write_config8(MEMCTRL, 0xd7, Data);
//step 30. normal SDRAM Mode - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x00; pci_write_config8(MEMCTRL, 0xd7, Data);
- Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data);
//step 31. exit the initialization mode - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xBF; pci_write_config8(MEMCTRL, 0xd3, Data);
//step 32. Enable bank paging and multi page - Data=pci_read_config8(MEMCTRL, 0x69); + Data = pci_read_config8(MEMCTRL, 0x69); Data |= 0x03; pci_write_config8(MEMCTRL, 0x69, Data); } @@ -878,7 +878,7 @@ Output : Void Purpose : Initialize DDR2 of CHC by standard sequence Reference : ===================================================================*/ -// DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) +// DDR2 CL = 2 CL = 3 CL = 4 CL = 5 (Burst type = interleave)(WR fine tune in code) static const u16 CHC_MRS_table[4] = { 0x22B, 0x23B, 0x24B, 0x25B }; // Use 1X-bandwidth MA table to init DRAM
void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr) diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h index 6fa1877..e4e143a 100644 --- a/src/northbridge/via/vx800/dram_init.h +++ b/src/northbridge/via/vx800/dram_init.h @@ -75,7 +75,7 @@ #define SPD_SDRAM_COL_ADDR 4 /*Number of column addresses on this assembly */ #define SPD_SDRAM_DIMM_RANKS 5 /*Number of RANKS on this assembly */ #define SPD_SDRAM_MOD_DATA_WIDTH 6 /*Data width of this assembly */ -#define SPD_SDRAM_TCLK_X 9 /*Cycle time at Maximum supported CAS latency (CL=X) */ +#define SPD_SDRAM_TCLK_X 9 /*Cycle time at Maximum supported CAS latency (CL = X) */ #define SPD_SDRAM_TAC_X 10 /*Access time for highest CL */ #define SPD_SDRAM_CONFIG_TYPE 11 /*Non-parity , Parity or ECC */ #define SPD_SDRAM_REFRESH 12 /*Refresh rate/type */ diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c index 634b8a8..b9466b9 100644 --- a/src/northbridge/via/vx800/drdy_bl.c +++ b/src/northbridge/via/vx800/drdy_bl.c @@ -42,14 +42,14 @@ // a.RDRPH(MD input internal timing control) // b.CAS Latency // RDELAYMD(1bit) = bit0 of (CL + RDRPH) -// for example: RDRPH=10b, CL3 -> F3_Rx56[5:4]=11b, 10b + 11b = 101b, RDELAYMD=1 (bit0) -// RDRPH=00b, CL2.5 -> F3_Rx56[5:4]=10b, 00b + 10b = 010b, RDELAYMD=0 (bit0) +// for example: RDRPH = 10b, CL3 -> F3_Rx56[5:4]=11b, 10b + 11b = 101b, RDELAYMD = 1 (bit0) +// RDRPH = 00b, CL2.5 -> F3_Rx56[5:4]=10b, 00b + 10b = 010b, RDELAYMD = 0 (bit0) // 2. CPU Frequency // 3. DRAM Frequency // // According to above conditions, we create different tables: -// 1. RDELAYMD=0 : for integer CAS latency(ex. CL=3) -// 2. RDELAYMD=1 : for non-integer CAS latency(ex. CL=2.5) +// 1. RDELAYMD = 0 : for integer CAS latency(ex. CL = 3) +// 2. RDELAYMD = 1 : for non-integer CAS latency(ex. CL = 2.5) // 3. Normal performance // 4. Top performance : // Using phase0 to a case has better performance. @@ -439,7 +439,7 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr) Data |= 0x08; pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data);
- //Data=pci_read_config8(PCI_DEV(0,0,2), 0x55); + //Data = pci_read_config8(PCI_DEV(0,0,2), 0x55); //Data = Data & (~0x20); //pci_write_config8(PCI_DEV(0,0,2), 0x55, Data);
@@ -538,17 +538,17 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr)
/*This routine process the ability for North Bridge side burst functionality There are 3 variances that are valid: - 1. DIMM BL=8, chipset BL=8 - 2. DIMM BL=4, chipset BL=4 - 3. DIMM BL=4, chipset BL=8 (only happened on Dual channel) + 1. DIMM BL = 8, chipset BL = 8 + 2. DIMM BL = 4, chipset BL = 4 + 3. DIMM BL = 4, chipset BL = 8 (only happened on Dual channel) Device 0 function 2 HOST:REG54[4] must be 1 when 128-bit mode. Since DIMM will be initialized in each rank individually, - 1.If all DIMM BL=4, DIMM will initialize BL=4 first, + 1.If all DIMM BL = 4, DIMM will initialize BL = 4 first, then check dual_channel flag to enable VIA_NB2HOST_REG54[4]. - 2.If all DIMM BL=8, DIMM will initialize BL=8 first, - then check dual_channel flag for re-initialize DIMM BL=4. + 2.If all DIMM BL = 8, DIMM will initialize BL = 8 first, + then check dual_channel flag for re-initialize DIMM BL = 4. also VIA_NB2HOST_REG54[4] need to be enabled. -Chipset_BL8==>chipset side can set burst length=8 +Chipset_BL8==>chipset side can set burst length = 8 two register need to set 1. Device 0 function 2 HOST:REG54[4] 2. Device 0 function 3 DRAM:REG6C[3] @@ -557,7 +557,7 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) { u8 Data, BL; u8 Sockets; - /*SPD byte16 bit3,2 describes the burst length supported. bit3=1 support BL=8 bit2=1 support BL=4 */ + /*SPD byte16 bit3,2 describes the burst length supported. bit3 = 1 support BL = 8 bit2 = 1 support BL = 4 */ BL = 0x0c; for (Sockets = 0; Sockets < 2; Sockets++) { if (DramAttr->DimmInfo[Sockets].bPresence) { @@ -568,9 +568,9 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) } }
- /*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL=4 ; =1 BL=8 */ + /*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL = 4 ; =1 BL = 8 */
- if (BL & 0x08) /*All Assembly support BL=8 */ + if (BL & 0x08) /*All Assembly support BL = 8 */ BL = 0x8; /*set bit3 */ else BL = 0x00; /*clear bit3 */ @@ -582,7 +582,7 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) if (DramAttr->RankNumChB > 0) { BL = DramAttr->DimmInfo[2].SPDDataBuf[SPD_SDRAM_BURSTLENGTH]; //Rx6c[1], CHB burst length - if (BL & 0x08) /*CHB support BL=8 */ + if (BL & 0x08) /*CHB support BL = 8 */ BL = 0x2; /*set bit1 */ else BL = 0x00; /*clear bit1 */ diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index dc2e1bd..6e11704 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -196,13 +196,13 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) }
/* cycle time value - 0x25-->2.5ns Freq=400 DDR800 - 0x30-->3.0ns Freq=333 DDR667 - 0x3D-->3.75ns Freq=266 DDR533 - 0x50-->5.0ns Freq=200 DDR400 - 0x60-->6.0ns Freq=166 DDR333 - 0x75-->7.5ns Freq=133 DDR266 - 0xA0-->10.0ns Freq=100 DDR200 + 0x25-->2.5ns Freq = 400 DDR800 + 0x30-->3.0ns Freq = 333 DDR667 + 0x3D-->3.75ns Freq = 266 DDR533 + 0x50-->5.0ns Freq = 200 DDR400 + 0x60-->6.0ns Freq = 166 DDR333 + 0x75-->7.5ns Freq = 133 DDR266 + 0xA0-->10.0ns Freq = 100 DDR200 */ if (CycTime <= 0x25) { DramAttr->DramFreq = DIMMFREQ_800; diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 00c1999..91197b5 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -108,7 +108,7 @@ static void setup_pm(device_t dev) /* set ACPI irq to 9 */ pci_write_config8(dev, 0x82, 0x49);
- /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ + /* Primary interupt channel, define wake events 0 = IRQ0 15 = IRQ15 1 = en. */ // pci_write_config16(dev, 0x84, 0x30f2); pci_write_config16(dev, 0x84, 0x609a); // 0x609a??
@@ -294,7 +294,6 @@ static void vx800_sb_init(struct device *dev) not called unless this device has a resource to set - so set a dummy one */ static void vx800_read_resources(device_t dev) { - struct resource *resource; pci_dev_read_resources(dev); resource = new_resource(dev, 1); @@ -336,8 +335,8 @@ static void southbridge_init(struct device *dev) fadt->p_lvl3_lat = 0x320;// fadt->pm2_cnt_len = 1;//to support cpu-c3 #2 - ssdt? ->every CPU has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC ) - #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. + ssdt? ->every CPU has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15 < 7:0>) to enter C3 state"---VIA vx800 P SPEC ) + #3 write 0x17 in to PMIO = VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. 1 enable SLP# asserts in C3 state PMIORx26<1> =1 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1 3 CLKRUN# is always asserted PMIORx26<3> =0 diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index 6cfb1b9..566aadf 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -141,7 +141,7 @@ void SetUMARam(void) pci_write_config8(vga_dev, 0xb2, ByteVal);
//set M1 size - //ByteVal=pci_read_config8(MEMCTRL, 0xa3); + //ByteVal = pci_read_config8(MEMCTRL, 0xa3); //ByteVal = 0x02; //pci_write_config8(MEMCTRL, 0xa3, ByteVal);
@@ -216,7 +216,7 @@ void SetUMARam(void) ByteVal = inb(0x03CC); ByteVal |= 0x03; outb(ByteVal, 0x03C2); - // ByteVal=inb(0x03C2); + // ByteVal = inb(0x03C2); // ByteVal |= 0x01; // outb(ByteVal,0x03C2);
@@ -318,7 +318,7 @@ void SetUMARam(void) outb(0x22, 0x03c5);
//start : For enable snapshot mode control - // program 3C5 for SNAPSHOT Mode control, set RxF3h=1Ah + // program 3C5 for SNAPSHOT Mode control, set RxF3h = 1Ah outb(0xf3, 0x03c4); ByteVal = inb(0x03c5); ByteVal = (ByteVal & 0xE5) | 0x1A; @@ -393,7 +393,7 @@ void SetUMARam(void) 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, };
- //for (i=0;i<0xc0;i++) + //for (i = 0; i < 0xc0; i++) for (i = 0; i < 0x40; i++) { outb(table3c0space[i], 0x03c0 + i); diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 61d4563..664e915 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -48,13 +48,13 @@
static int via_vx800_int15_handler(void) { - int res=0; + int res = 0; printk(BIOS_DEBUG, "via_vx800_int15_handler\n"); switch(X86_EAX & 0xffff) { case 0x5f19: - X86_EAX=0x5f; - X86_ECX=0x03; - res=1; + X86_EAX = 0x5f; + X86_ECX = 0x03; + res = 1; break; case 0x5f18: { @@ -104,11 +104,11 @@ static int via_vx800_int15_handler(void) res = 1; break; case 0x5f02: - X86_EAX=0x5f; - X86_EBX= (X86_EBX & 0xffff0000) | 2; - X86_ECX= (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only - X86_EDX= (X86_EDX & 0xffff0000) | 0; // TV Layout - default - res=1; + X86_EAX = 0x5f; + X86_EBX = (X86_EBX & 0xffff0000) | 2; + X86_ECX = (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only + X86_EDX = (X86_EDX & 0xffff0000) | 0; // TV Layout - default + res = 1; break; case 0x5f0f: X86_EAX = 0x005f;