Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51258 )
Change subject: mb/google/brya: brya0: Add ACPI support for Type-C ports ......................................................................
mb/google/brya: brya0: Add ACPI support for Type-C ports
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Ic201ad047fd0d593749d2b993f843f7e188a5c98 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/dsdt.asl M src/mainboard/google/brya/variants/brya0/overridetree.cb 3 files changed, 27 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/51258/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index d0391af..17dab64 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -5,6 +5,7 @@ select DRIVERS_I2C_HID select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_SX9324 + select DRIVERS_INTEL_PMC select DRIVERS_SPI_ACPI select DRIVERS_WIFI_GENERIC select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index 5d386f1..f37d6b8 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -26,6 +26,7 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> } }
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index aa5dc8f..4440ba8 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -199,10 +199,34 @@ end device ref pch_espi on chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] device pnp 0c09.0 on end end end - device ref pmc hidden end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "1" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "2" + register "usb3_port_number" = "2" + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "3" + device generic 2 alias conn2 on end + end + end + end + end device ref tcss_xhci on chip drivers/usb/acpi device ref tcss_root_hub on