[coreboot-gerrit] Patch merged into coreboot/master: dae15a6 rk3288: Add early SRAM mapping

the following patch was just integrated into master:
commit dae15a63e426230117b575f9acc504110748e98f
Author: Julius Werner 
Date:   Wed Oct 15 18:50:45 2014 -0700

rk3288: Add early SRAM mapping

Solving the DACR bug will mean that XN bits suddenly become enforced on
    non-LPAE systems, and we will no longer be able to execute out of a
    region mapped DCACHE_OFF. When we enable the MMU in romstage we are
    still executing out of SRAM, so we would instantly kill ourselves.

Solve this issue by enabling the MMU earlier (in the bootblock) and
    mapping the SRAM regions as DCACHE_WRITETHROUGH. They should really be
    DCACHE_WRITEBACK, but it looks like there might be hardware limitations
    in the Cortex-A12 cache architecture that prevent us from doing so.
    Write-through mappings are equivalent to normal non-cacheable on the A12
    anyway, and by using this attribute we don't need to introduce a new
    DCACHE_OFF_BUT_WITHOUT_XN_BIT type in our API. (Also, using normal
    non-cacheable might still have a slight speed advantage over strongly
    ordered since it should fetch whole cache lines at once if the processor
    finds enough accesses it can combine.)

CQ-DEPEND=CL:223783
    BUG=chrome-os-partner:32118
    TEST=None (depends on follow-up CL)

Change-Id: I1e5127421f82177ca11af892b1539538b379625e
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: e7b079f4b6a69449f3c7cc18ef0e1704f2006847
    Original-Change-Id: I53e827d95acc2db909f1251de78d65e295eceaa7
    Original-Signed-off-by: Julius Werner 
    Original-Reviewed-on: https://chromium-review.googlesource.com/223782
    Original-Reviewed-by: Aaron Durbin 
    Reviewed-on: http://review.coreboot.org/9342
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer

See http://review.coreboot.org/9342 for details.

-gerrit