Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43094 )
Change subject: nb/intel/haswell: Add `mb_late_romstage_setup` function ......................................................................
nb/intel/haswell: Add `mb_late_romstage_setup` function
This function is called at the end of `romstage_common`. Only one board makes use of it, the Lenovo ThinkPad T440p. To preserve behavior, call it after `romstage_common` has done nearly everything.
Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43094 Reviewed-by: Tristan Corrick tristan@corrick.kiwi Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/lenovo/t440p/romstage.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/romstage.c 3 files changed, 27 insertions(+), 17 deletions(-)
Approvals: build bot (Jenkins): Verified Tristan Corrick: Looks good to me, approved
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index bd1020d..900bef5 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -23,6 +23,26 @@ RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); }
+void mb_late_romstage_setup(void) +{ + u8 enable_peg; + if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) + enable_peg = 0; + + bool power_en = pmh7_dgpu_power_state(); + + if (enable_peg != power_en) + pmh7_dgpu_power_enable(!power_en); + + if (!enable_peg) { + // Hide disabled dGPU device + u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~DEVEN_D1F0EN; + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); + } +} + void mainboard_romstage_entry(void) { struct pei_data pei_data = { @@ -77,21 +97,4 @@ };
romstage_common(&romstage_params); - - u8 enable_peg; - if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) - enable_peg = 0; - - bool power_en = pmh7_dgpu_power_state(); - - if (enable_peg != power_en) - pmh7_dgpu_power_enable(!power_en); - - if (!enable_peg) { - // Hide disabled dGPU device - u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~DEVEN_D1F0EN; - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); - } } diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index fa32eca..7fb24c8 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -195,6 +195,7 @@ void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); +void mb_late_romstage_setup(void); /* optional */
void haswell_early_initialization(void); void haswell_late_initialization(void); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 8cf2e7c..ae9d707 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -13,6 +13,10 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/me.h>
+void __weak mb_late_romstage_setup(void) +{ +} + void romstage_common(const struct romstage_params *params) { int wake_from_s3; @@ -77,5 +81,7 @@
romstage_handoff_init(wake_from_s3);
+ mb_late_romstage_setup(); + post_code(0x3f); }