[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: fix use of legacy 8254 timer

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33512 )

Change subject: soc/intel/cannonlake: fix use of legacy 8254 timer
......................................................................

soc/intel/cannonlake: fix use of legacy 8254 timer

FSP sets the use of the 8254 timer via the Enable8254ClockGating
UPD, which defaults to enabled, overriding what is set by coreboot.
Per the FSP integration guide, this UPD needs to be disabled when
a legacy OS is booted (ie, when SeaBIOS is used as the payload).

Add a Kconfig option to set the UPD properly based on payload
selection, and remove the existing coreboot code in lpc.c since
it is either ineffective or being overridden by FSP.

Test: build/boot out-of-tree WHL board with both SeaBIOS and
Tianocore, ensure 8254 timer usage set correctly for each.

Signed-off-by: Matt DeVillier 
Change-Id: I0e888bf754cb72093f14fc02f39bddcd6d288203
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33512
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/lpc.c
4 files changed, 12 insertions(+), 13 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 2279df2..679efce 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -314,4 +314,12 @@
      Setting non-zero value will allow to use DBC or DCI to debug SOC.
      PlatformDebugConsent in FspmUpd.h has the details.

+config USE_LEGACY_8254_TIMER
+	bool "Use Legacy 8254 Timer"
+	default y if PAYLOAD_SEABIOS
+	default n
+	help
+	  This sets the Enable8254ClockGating UPD, which according to the FSP Integration
+	  guide needs to be disabled in order to boot SeaBIOS, but should otherwise be enabled.
+
 endif
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 3b4c980..71aa208 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -246,8 +246,6 @@
    /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
    uint8_t eist_enable;

-	/* Statically clock gate 8254 PIT. */
-	uint8_t clock_gate_8254;
    /* Enable C6 DRAM */
    uint8_t enable_c6dram;
    /*
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index dd93882..783ebb7 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -244,6 +244,10 @@
    /* disable Legacy PME */
    memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));

+	/* Legacy 8254 timer support */
+	params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
+	params->Enable8254ClockGatingOnS3 = 1;
+
    /* USB */
    for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
    	params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index 56fefa5..6cc3451 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -207,16 +207,6 @@
    outb(0x70, (1 << 7));
 };

-static void clock_gate_8254(const struct device *dev)
-{
-	const config_t *config = dev->chip_info;
-
-	if (!config->clock_gate_8254)
-		return;
-
-	itss_clock_gate_8254();
-}
-
 void lpc_soc_init(struct device *dev)
 {
    /* Legacy initialization */
@@ -237,7 +227,6 @@
    soc_pch_pirq_init(dev);
    setup_i8259();
    i8259_configure_irq_trigger(9, 1);
-	clock_gate_8254(dev);
    soc_mirror_dmi_pcr_io_dec();
 }