Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Ravishankar Sarawadi, Saurabh Mishra, Tarun.
Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 53:
(3 comments)
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/fc8bc271_e719868f?usp... :
PS51, Line 19: #define SAF_BASE_ADDRESS 0x3ffe000000
: #define SAF_BASE_SIZE 0x2000000
We, , this is correct, SAF is moved below 4GB, but since there's a difficulty in sharing the intel restricted doc to be verified by you, i.e. FASv1.1, ideal way is to mark as "To-Do" and update with the previous value. Once the doc is ready to be sharing, we will update this to the newwer FAS aligned value. Let me know if this works?
In that case, can you please add a TODO here ?
File src/soc/intel/pantherlake/soc_info.c:
https://review.coreboot.org/c/coreboot/+/83354/comment/b216798f_ab59cee4?usp... :
PS53, Line 31: CONFIG_MAX_ROOT_PORTS
where is this getting defined ? can you please check
you overlooked my review comment
https://review.coreboot.org/c/coreboot/+/83354/comment/6a9e0864_1f276911/
```
the same logic applies to others as well
```
https://review.coreboot.org/c/coreboot/+/83354/comment/e276ddd4_1f1585ce?usp... :
PS53, Line 36: CONFIG_MAX_PCIE_CLOCK_SRC
where is this getting defined ? can you please check
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