Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84997?usp=email )
Change subject: mb/google/nissa/var/rull: add touchpad init config and change ssd timeing ......................................................................
mb/google/nissa/var/rull: add touchpad init config and change ssd timeing
We initialize the touchpad initialization configuration. At the same time, the previous GPIO configuration will cause the SSD device to not be recognized. We adjust the position of the enable and reset pins.
BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power on proto board successfully 3. touchpad
Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab --- M src/mainboard/google/brya/variants/rull/gpio.c M src/mainboard/google/brya/variants/rull/overridetree.cb M src/mainboard/google/brya/variants/rull/variant.c 3 files changed, 55 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84997/1
diff --git a/src/mainboard/google/brya/variants/rull/gpio.c b/src/mainboard/google/brya/variants/rull/gpio.c index 13d6469..03cadaa 100644 --- a/src/mainboard/google/brya/variants/rull/gpio.c +++ b/src/mainboard/google/brya/variants/rull/gpio.c @@ -23,14 +23,17 @@ /* A22 : GPP_A22 ==> NC */ PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
- /* B4 : I2C2_SDA ==> SSD1_RST_L */ - PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* B5 : I2C2_SDA ==> NA */ PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), /* B6 : I2C2_SCL ==> NA */ PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), /* B11 : NC ==> EN_PP3300_WLAN_X*/ - PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_GPO(GPP_B11, 1, DEEP), + + /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
/* D3 : ISH_GP3 ==> NA */ PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), @@ -38,8 +41,7 @@ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* D8 : SRCCLKREQ3# ==> NC */ PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), - /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* D13 : EN_PP1800_WCAM_X ==> NA */ PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D15 : EN_PP2800_WCAM_X ==> NA */ @@ -56,6 +58,8 @@ /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */ PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
+ /* F11 : NC ==> WWAN_PWR_ON */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), /* F12 : WWAN_RST_L ==> NA */ PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), /* F13 : SOC_PEN_DETECT_R_ODL ==> NA */ @@ -78,7 +82,9 @@ PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG), /* H23 : WWAN_SAR_DETECT_ODL ==> NA */ PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG), - + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */ @@ -105,6 +111,9 @@
/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* B4 : I2C2_SDA ==> SSD1_RST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
@@ -116,11 +125,6 @@ /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
- /* F11 : NC ==> WWAN_PWR_ON */ - PAD_CFG_GPO(GPP_F11, 1, DEEP), - /* F12 : GSXDOUT ==> WWAN_RST_L */ - PAD_CFG_GPO(GPP_F12, 0, DEEP), - /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ @@ -132,9 +136,12 @@ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), };
static const struct pad_config romstage_gpio_table[] = { + };
const struct pad_config *variant_gpio_override_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index d91a7aa..b59a0de 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -231,7 +231,27 @@ device i2c 1a on end end end - device ref i2c5 off end # Touchpad + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""PIXART Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 68 on end + end + end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" @@ -254,6 +274,13 @@ register "add_acpi_dma_property" = "true" device pci 00.0 on end end + chip soc/intel/common/block/pcie/rtd3 + # # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on end + end probe WIFI WIFI_PCIE_WIFI7 probe unprovisioned end @@ -405,13 +432,14 @@ }" chip soc/intel/common/block/pcie/rtd3 # enable_gpio is EN_PP3300_SSD - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D11)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" register "srcclk_pin" = "1" - device generic 0 on end + device generic 0 on + probe STORAGE STORAGE_NVME + probe unprovisioned + end end - probe STORAGE STORAGE_NVME - probe unprovisioned end device ref emmc on probe STORAGE STORAGE_EMMC diff --git a/src/mainboard/google/brya/variants/rull/variant.c b/src/mainboard/google/brya/variants/rull/variant.c index a2fffb4..1f51c09 100644 --- a/src/mainboard/google/brya/variants/rull/variant.c +++ b/src/mainboard/google/brya/variants/rull/variant.c @@ -16,29 +16,12 @@ return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); }
-static const struct pad_config wifi_pcie_enable_pad[] = { - /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ - PAD_CFG_GPO(GPP_H20, 1, DEEP), - /* B11 : NC ==> EN_PP3300_WLAN_X*/ - PAD_CFG_GPO(GPP_B11, 1, DEEP), -}; - void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - if (!fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || fw_config_is_provisioned()) { - printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n"); - config->cnvi_bt_core = false; - printk(BIOS_INFO, "CNVi bluetooth audio offload disabled by fw_config\n"); - config->cnvi_bt_audio_offload = false; - } -} - -void fw_config_gpio_padbased_override(struct pad_config *padbased_table) -{ if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || !fw_config_is_provisioned()) { - printk(BIOS_INFO, "Enable PCie based Wifi GPIO pins.\n"); - gpio_padbased_override(padbased_table, wifi_pcie_enable_pad, - ARRAY_SIZE(wifi_pcie_enable_pad)); + printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); + config->cnvi_bt_core = true; + config->cnvi_bt_audio_offload = true; } }