[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57465 )

Change subject: soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU
......................................................................

soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU

There are two different types of 282 SKU available with TDP
of 15W and 12W for Alder Lake-M SoC. This patch adds support
for these TDP values for 282 SKU as per document 643782.

BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board

Change-Id: I553b2362b7bf811e6bf02fd9d68f78c2caeb7398
Signed-off-by: Sumeet Pawnikar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57465
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Selma Bensaid 
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/chipset.cb
2 files changed, 11 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved
  Selma Bensaid: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 6308094..3192478 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -25,7 +25,8 @@
    ADL_P_482_CORE,
    ADL_P_682_28W_CORE,
    ADL_P_682_45W_CORE,
-	ADL_M_282_CORE,
+	ADL_M_282_12W_CORE,
+	ADL_M_282_15W_CORE,
    ADL_M_242_CORE,
    ADL_P_242_CORE,
    ADL_POWER_LIMITS_COUNT
@@ -34,6 +35,7 @@
 /* TDP values for different SKUs */
 enum soc_intel_alderlake_cpu_tdps {
    TDP_9W  = 9,
+	TDP_12W = 12,
    TDP_15W = 15,
    TDP_28W = 28,
    TDP_45W = 45
@@ -50,7 +52,8 @@
    { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W },
    { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W },
    { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W },
-	{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_CORE, TDP_15W },
+	{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W },
+	{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
    { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },
 };

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index d70d939..9a752dd 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -26,7 +26,12 @@
    	.tdp_pl4 = 215,
    }"

-	register "power_limits_config[ADL_M_282_CORE]" = "{
+	register "power_limits_config[ADL_M_282_12W_CORE]" = "{
+		.tdp_pl1_override = 12,
+		.tdp_pl2_override = 35,
+	}"
+
+	register "power_limits_config[ADL_M_282_15W_CORE]" = "{
    	.tdp_pl1_override = 15,
    	.tdp_pl2_override = 45,
    }"