Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75824?usp=email )
Change subject: ec/google/chromeec: Use mux_conn to get the right USB port ......................................................................
ec/google/chromeec: Use mux_conn to get the right USB port
get_usb_port_references only work while all the port assign by order. If the port assign cross ports like mux[0] use USB3 and mux[1] use USB1, it still connect mux[0] to USB1.
BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. before patch: Package (0x02) { "usb2-port", _SB.PCI0.XHCI.RHUB.HS01 },
Package (0x02) { "usb3-port", _SB.PCI0.TXHC.RHUB.SS01 }, after patch: Package (0x02) { "usb2-port", _SB.PCI0.XHCI.RHUB.HS01 },
Package (0x02) { "usb3-port", _SB.PCI0.TXHC.RHUB.SS03 },
Signed-off-by: Eric Lai eric_lai@quanta.corp-partner.google.com Change-Id: I058c6cc0fea6758bfaafdd163b5da2c7f75daf8a --- M src/ec/google/chromeec/ec_acpi.c 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/75824/1
diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 53a4e75..da772d4 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -12,6 +12,7 @@ #include <ec/google/common/dptf.h>
#include "chip.h" +#include "drivers/intel/pmc_mux/conn/chip.h" #include "ec.h" #include "ec_commands.h"
@@ -182,6 +183,13 @@ usb4_port = NULL; get_usb_port_references(i, &usb2_port, &usb3_port, &usb4_port);
+ if (CONFIG(DRIVERS_INTEL_PMC)) { + struct drivers_intel_pmc_mux_conn_config *conn_config = + config->mux_conn[i]->chip_info; + usb2_port = conn_config->usb2_port; + usb3_port = conn_config->usb3_port; + } + get_pld_from_usb_ports(&pld, usb2_port, usb3_port, usb4_port);
struct typec_connector_class_config typec_config = {