Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42440 )
Change subject: soc/intel/cannonlake: Add PchPmPwrCycDur to chip options ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/fs... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/fs... PS3, Line 415: PchPmPwrCycDur
I think its safer to have a sanity check since it is clearly in violation of the EDS if the PwrCycDu […]
Thing is, supported minimum assertion duration list of a signal varies from micro seonds to seconds. For example, if we see PchPmSlpS3MinAssert's supported min. assertion duration list : /* slp_s3_asst_dur_list: 50ms, 60us, 1ms, 50ms (Default), 2s */ slp_s3_asst_dur_list[] = { 0.05, 0.00006, 0.001, 0.05, 2}; Note: Index value points to PchPmSlpS3MinAssert UPD value
So, we have to normalize the assertion duration of these signal's duration list into one common unit(either seconds or usec) to find higher assertion width. This translates list values into floating points if we convert lists into seconds. Othewise bigger number if we represent durations into useconds. So, that's why I prefer documenting while documenting EDS recommendation.