Attention is currently required from: Tarun Tuli.
Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72872 )
Change subject: mb/google/brya/var/omnigul: Modify variant specific devicetree ......................................................................
mb/google/brya/var/omnigul: Modify variant specific devicetree
add SoC config and .early_init = 1 in I2C1
BUG=b:263060849 TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I661bdee6c7b9e6ea4cd0ab2006967d7c7ddd0f67 Signed-off-by: Jamie Chen jamie_chen@compal.corp-partner.google.com --- M src/mainboard/google/brya/variants/omnigul/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/72872/1
diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb index d243668..84fe0bb 100644 --- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -9,6 +9,34 @@ chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | TouchScreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }"
register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci,