Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59306 )
Change subject: soc/intel/common: Include Alder Lake-N device IDs ......................................................................
soc/intel/common: Include Alder Lake-N device IDs
Add Alder Lake-N specific CPU, System Agent, PCH (Alder Point aka ADP), IGD device IDs.
Document Number: 619501, 645548
Signed-off-by: Usha P usha.p@intel.com Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59306 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/systemagent/systemagent.c 6 files changed, 20 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 5314076..0f7c5c1 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -55,5 +55,6 @@ #define CPUID_ALDERLAKE_A1 0x906a1 #define CPUID_ALDERLAKE_A2 0x906a2 #define CPUID_ALDERLAKE_A3 0x906a4 +#define CPUID_ALDERLAKE_N_A0 0xb06e0
#endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 63b735f..db51905 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3886,6 +3886,10 @@ #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 #define PCI_DEVICE_ID_INTEL_ADL_M_GT2 0x46aa #define PCI_DEVICE_ID_INTEL_ADL_M_GT3 0x46c3 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT1 0x46D0 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT2 0x46D1 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT3 0x46D2 +
/* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3997,6 +4001,9 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f #define PCI_DEVICE_ID_INTEL_ADL_M_ID_1 0x4602 #define PCI_DEVICE_ID_INTEL_ADL_M_ID_2 0x460a +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_1 0x4617 +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_2 0x461B + /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22 #define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 2fc8eab..76e6c80 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -27,6 +27,7 @@ { CPUID_ALDERLAKE_A1, "Alderlake Platform" }, { CPUID_ALDERLAKE_A2, "Alderlake Platform" }, { CPUID_ALDERLAKE_A3, "Alderlake Platform" }, + { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" }, };
static struct { @@ -43,6 +44,8 @@ { PCI_DEVICE_ID_INTEL_ADL_P_ID_9, "Alderlake-P" }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, "Alderlake-M" }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, "Alderlake-M" }, + { PCI_DEVICE_ID_INTEL_ADL_N_ID_1, "Alderlake-N" }, + { PCI_DEVICE_ID_INTEL_ADL_N_ID_2, "Alderlake-N" }, };
static struct { @@ -111,6 +114,9 @@ { PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" }, { PCI_DEVICE_ID_INTEL_ADL_M_GT2, "Alderlake M GT2" }, { PCI_DEVICE_ID_INTEL_ADL_M_GT3, "Alderlake M GT3" }, + { PCI_DEVICE_ID_INTEL_ADL_N_GT1, "Alderlake N GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_N_GT2, "Alderlake N GT2" }, + { PCI_DEVICE_ID_INTEL_ADL_N_GT3, "Alderlake N GT3" }, };
static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index acd15a8..b7e2243 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -72,6 +72,7 @@ { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A1 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A2 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A3 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0}, { 0, 0 }, };
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index e7e96ad..1db0e46 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -311,6 +311,9 @@ PCI_DEVICE_ID_INTEL_ADL_M_GT1, PCI_DEVICE_ID_INTEL_ADL_M_GT2, PCI_DEVICE_ID_INTEL_ADL_M_GT3, + PCI_DEVICE_ID_INTEL_ADL_N_GT1, + PCI_DEVICE_ID_INTEL_ADL_N_GT2, + PCI_DEVICE_ID_INTEL_ADL_N_GT3, 0, };
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 572b417..b7c6d4f 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -435,6 +435,8 @@ PCI_DEVICE_ID_INTEL_ADL_P_ID_9, PCI_DEVICE_ID_INTEL_ADL_M_ID_1, PCI_DEVICE_ID_INTEL_ADL_M_ID_2, + PCI_DEVICE_ID_INTEL_ADL_N_ID_1, + PCI_DEVICE_ID_INTEL_ADL_N_ID_2, 0 };
2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.