[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions

[Cliff Huang (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )

Change subject: soc/intel/common/block/pmc: Add GPE1 functions
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Patch Set 8:

(2 comments)

File src/soc/intel/common/block/pmc/pmclib.c:

https://review.coreboot.org/c/coreboot/+/84104/comment/0c30d326_f4de1747?usp... :
PS8, Line 321: 	soc_pmc_disable_std_gpe1(mask);
Subrata,

In PTL, in the case that we choose not to switch to use GPE1 events (i.e. not include GPE1 in FADT so that kernel won't see GPE1 event and include only ACPI GPE0 event methods in DSDT/SSDT), these GPE1 status bit might still be set by the HW and we need to clear it at boot. We might need to go back to use _HAVE_GPE1 and _USE_GPE1 approach.

_USE_GPE1: if false:  _USE_GEP1: dummy GPE_STS defines. include GPE0 methods.

if true: add GPE1 blocks to FADT and include GPE1 methods

_HAVE_GPE1: 
            define GPE_STS() in SOC.
            clear GPE1 STS at boot.

acpi.c:
     fadt->gpe1_blk = CONFIG(_USE_GPE1) ? (pmbase + GPE1_STS(0)) : 0;

also, in acpi Kconfig
_USE_GPE1 depends on _HAVE_GPE1 as you mentioned in one of comments.

Any thought prior to https://review.coreboot.org/c/coreboot/+/84103/14 being merged?

https://review.coreboot.org/c/coreboot/+/84104/comment/8fb77c5c_fc6d977c?usp... :
PS8, Line 330: 	if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1))
same reason for pmc_disable_std_gpe()