Attention is currently required from: Martin Roth, Patrick Rudolph. HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49507 )
Change subject: [test] (i945;LGA775): Add x86_64 support ......................................................................
[test] (i945;LGA775): Add x86_64 support
not tested on hardware
Change-Id: I59260b34b223b3ae247dc1860eb94684bba867fa Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/car/cache_as_ram_symbols.inc M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/rcven.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/early_init.c 8 files changed, 37 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49507/1
diff --git a/src/cpu/intel/car/cache_as_ram_symbols.inc b/src/cpu/intel/car/cache_as_ram_symbols.inc index 857e039..97f3d24 100644 --- a/src/cpu/intel/car/cache_as_ram_symbols.inc +++ b/src/cpu/intel/car/cache_as_ram_symbols.inc @@ -18,3 +18,9 @@
car_mtrr_start: .uintptr_t _car_mtrr_start + +xip_mtrr_mask: +.uintptr_t _xip_mtrr_mask + +car_mtrr_size: +.uintptr_t _car_mtrr_size diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 103d9e9..af4d527 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -11,6 +11,8 @@ .section .init .global bootblock_pre_c_entry
+#include <cpu/intel/car/cache_as_ram_symbols.inc> + .code32 _cache_as_ram_setup:
@@ -212,7 +214,7 @@
/* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx - movl $_car_mtrr_start, %eax + movl car_mtrr_start, %eax orl $MTRR_TYPE_WRBACK, %eax xorl %edx, %edx wrmsr @@ -220,7 +222,7 @@ /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + movl car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
@@ -272,12 +274,12 @@ /* Cache the whole rom to fetch microcode updates */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $_rom_mtrr_base, %eax + movl rom_mtrr_base, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_rom_mtrr_mask, %eax + movl rom_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
@@ -324,12 +326,12 @@ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx movl $_program, %eax - andl $_xip_mtrr_mask, %eax + andl xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_xip_mtrr_mask, %eax + movl xip_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
@@ -344,8 +346,8 @@ /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax - movl $_car_mtrr_start, %edi - movl $_car_mtrr_size, %ecx + movl car_mtrr_start, %edi + movl car_mtrr_size, %ecx shr $2, %ecx rep stosl
@@ -356,7 +358,14 @@ the pushes below. */ andl $0xfffffff0, %esp subl $4, %esp - +#if ENV_X86_64 + #include <cpu/x86/64bit/entry64.inc> + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else /* push TSC and BIST to stack */ movd %mm0, %eax pushl %eax /* BIST */ @@ -364,6 +373,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif
before_c_entry: post_code(0x2f) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index b396eff..4859598 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -73,7 +73,7 @@
static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, - u8 *mmiobase, unsigned int pgfx) + u8 *mmiobase, uintptr_t pgfx) { struct edid edid; struct edid_mode *mode; @@ -95,7 +95,7 @@
printk(BIOS_SPEW, "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", - (void *)pgfx, mmiobase, piobase, pphysbase); + (void *)(uintptr_t)pgfx, mmiobase, piobase, pphysbase);
intel_gmbus_read_edid(mmiobase + GMBUS0, GMBUS_PORT_PANEL, 0x50, edid_data, sizeof(edid_data)); @@ -356,8 +356,8 @@
if (CONFIG(LINEAR_FRAMEBUFFER)) { printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", - (void *)pgfx, hactive * vactive * 4); - memset((void *)pgfx, 0x00, hactive * vactive * 4); + (void *)(uintptr_t)pgfx, hactive * vactive * 4); + memset((void *)(uintptr_t)pgfx, 0x00, hactive * vactive * 4);
fb_new_framebuffer_info_from_edid(&edid, pgfx); } else { @@ -373,7 +373,7 @@
static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, - u8 *mmiobase, unsigned int pgfx) + u8 *mmiobase, uintptr_t pgfx) { int i; u32 hactive, vactive; @@ -381,7 +381,7 @@ u32 uma_size;
printk(BIOS_SPEW, "mmiobase %x addrport %x physbase %x\n", - (u32)mmiobase, piobase, pphysbase); + (u32)(uintptr_t)mmiobase, piobase, pphysbase);
gtt_setup(mmiobase);
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index cfa527f..dc2408d 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -93,7 +93,7 @@
/* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - cbmem_topk = ((uint32_t)cbmem_top() >> 10); + cbmem_topk = ((uintptr_t)cbmem_top() >> 10); delta_cbmem = tomk_stolen - cbmem_topk; tomk_stolen -= delta_cbmem;
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a1a9a9c..7969565 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -70,7 +70,7 @@ udelay(1); }
-static void ram_read32(u32 offset) +static void ram_read32(uintptr_t offset) { PRINTK_DEBUG(" RAM read: %08x\n", offset);
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index 0b58904..796de22 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -10,7 +10,8 @@ */ static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo) { - u32 reg32, addr; + u32 reg32; + uintptr_t addr; int i;
MCHBAR32(C0DRC1 + channel_offset) |= (1 << 6); diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 3ace204..9bbe8d6 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -192,7 +192,7 @@ // NOTE this will break as soon as the Azalia get's a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); codec_mask = codec_detect(base);
if (codec_mask) { diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 72281ea..8aeca2c 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -48,7 +48,7 @@ void i82801gx_setup_bars(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); - pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN);