[coreboot-gerrit] [S] Change in coreboot[master]: cpu/intel/socket_mPGA604: Drop implicit SSE/SSE2

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69443 )

Change subject: cpu/intel/socket_mPGA604: Drop implicit SSE/SSE2
......................................................................

cpu/intel/socket_mPGA604: Drop implicit SSE/SSE2

The disablement of SSE2 was not honoured since there is explicit
select under CPU_INTEL_MODEL_F2X. The removed commentary originates
probably from ROMCC romstage implementation.

Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/intel/socket_mPGA604/Kconfig
1 file changed, 14 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/69443/1

diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index 7b08699..12c8e37 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -7,20 +7,12 @@
    def_bool y
    select CPU_INTEL_MODEL_F2X
    select MMX
-	select SSE
    select UDELAY_TSC
    select TSC_MONOTONIC_TIMER
    select SIPI_VECTOR_IN_ROM
    select CPU_INTEL_COMMON
    select CPU_INTEL_COMMON_TIMEBASE

-# mPGA604 are usually Intel Netburst CPUs which should have SSE2
-# but the ramtest.c code on the Dell S1850 seems to choke on
-# enabling it, so disable it for now.
-config SSE2
-	bool
-	default n
-
 config DCACHE_RAM_BASE
    hex
    default 0xfefc0000