Attention is currently required from: Angel Pons, Felix Singer, Matt DeVillier, Michael Niewöhner, Tim Wawrzynczak.
Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75090?usp=email )
Change subject: mb/purism/librem_l1um_v2: Add support for Purism Librem L1UM v2 ......................................................................
Patch Set 4:
(14 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75090/comment/7f35c010_84897e91 : PS1, Line 24: - VGA BIOS
I did not know there was native VGA for AST2500! Thanks, I will look into this!
Done
File src/mainboard/purism/librem_l1um_v2/Kconfig:
https://review.coreboot.org/c/coreboot/+/75090/comment/d7c8a30d_8805c38e : PS1, Line 3: select SOC_INTEL_COFFEELAKE : select BOARD_ROMSIZE_KB_32768 : select DRIVERS_UART_8250IO : select GENERATE_SMBIOS_TABLES : select HAVE_ACPI_TABLES : select IPMI_KCS : select MEMORY_MAPPED_TPM : select SOC_INTEL_CANNONLAKE_PCH_H : select SUPERIO_ASPEED_COMMON_PRE_RAM : select SUPERIO_ASPEED_AST2400 : select DRIVERS_ASPEED_AST_COMMON : select DRIVERS_ASPEED_AST2050 : select SUPERIO_NUVOTON_NCT6791D # This board has two SuperIOs : select DRIVERS_GENERIC_CBFS_SERIAL : select DRIVERS_USB_ACPI : select MAINBOARD_HAS_TPM2 : select SMBIOS_TYPE41_PROVIDED_BY_DEVTREE
Ack
Done
File src/mainboard/purism/librem_l1um_v2/board_info.txt:
https://review.coreboot.org/c/coreboot/+/75090/comment/d25e26e0_e4d6ceac : PS1, Line 3: misc
Ack
Done
File src/mainboard/purism/librem_l1um_v2/bootblock.c:
https://review.coreboot.org/c/coreboot/+/75090/comment/f755d15d_4502cee0 : PS1, Line 17: int64_t bmc_ready_elapsed = 0;
Ack
Done
File src/mainboard/purism/librem_l1um_v2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/75090/comment/a291add2_c1624f7d : PS1, Line 3: register "SataSalpSupport" = "0"
Ack
Done
https://review.coreboot.org/c/coreboot/+/75090/comment/dbdd1cd9_021d205e : PS1, Line 4: register "satapwroptimize" = "1"
Ack
Done
https://review.coreboot.org/c/coreboot/+/75090/comment/92beb401_a1ac7b87 : PS1, Line 8: register "SataPortsEnable[0]" = "1" : register "SataPortsEnable[1]" = "1" : register "SataPortsEnable[2]" = "1" : register "SataPortsEnable[3]" = "1" : register "SataPortsEnable[4]" = "1" : register "SataPortsEnable[5]" = "1" : register "SataPortsEnable[6]" = "1" : register "SataPortsEnable[7]" = "1" : : register "SataPortsHotPlug[0]" = "1" : register "SataPortsHotPlug[1]" = "1" : register "SataPortsHotPlug[2]" = "1" : register "SataPortsHotPlug[3]" = "1" : register "SataPortsHotPlug[4]" = "1" : register "SataPortsHotPlug[5]" = "1" : register "SataPortsHotPlug[6]" = "1" : register "SataPortsHotPlug[7]" = "1"
Ack
Done
https://review.coreboot.org/c/coreboot/+/75090/comment/d2042f8c_7fbe8fbc : PS1, Line 26: register "PchHdaDspEnable" = "0" : register "PchHdaAudioLinkHda" = "0"
Ack
Done
https://review.coreboot.org/c/coreboot/+/75090/comment/1e2e022e_e23deea5 : PS1, Line 46: register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 front left : register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 front right : register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB_1_2 header port A : register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB_1_2 header port B : register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 rear top-right : register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 rear bottom-right : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # BMC port A : register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 rear bottom-left : register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BMC port B (seems to be unused) : register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 rear top-left : : register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 rear bottom-right : register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 rear top-right : register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 rear bottom-left : register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 rear top-left : register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 front left : register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 front right
Ack
Done
https://review.coreboot.org/c/coreboot/+/75090/comment/af3dd749_6a78c5d6 : PS1, Line 69: [PchSerialIoIndexI2C0] = PchSerialIoPci, : [PchSerialIoIndexI2C1] = PchSerialIoPci,
If `PchSerialIoDisabled` equalz 0, you can remove the entire array from the devicetree.
It doesn't, 0 is `PchSerialIoNotInitialized`, so we need to keep this. https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src...
https://review.coreboot.org/c/coreboot/+/75090/comment/5e62fb48_e0441ff2 : PS1, Line 82: # This board has a lot of SuperIO LDNs with I/O BARs, the LPC generic : # I/O ranges must be configured manually. : register "gen1_dec" = "0x000c0ca1" # IPMI: ca0-caf : register "gen2_dec" = "0x007c0a01" # ASpeed SuperIO SWC and mailbox: a00-a7f : register "gen3_dec" = "0x00040291" # Nuvoton SuperIO HW monitor: 290-297 : : # AST2500 Super IO UART1 requires continuous mode : register "serirq_mode" = "SERIRQ_CONTINUOUS"
Ack
Done
https://review.coreboot.org/c/coreboot/+/75090/comment/e96b42ca_f9050d6c : PS1, Line 216: device pci 15.0 on end # I2C #0 : device pci 15.1 on end # I2C #1
Ack
Done
https://review.coreboot.org/c/coreboot/+/75090/comment/9c662c17_ea504ab5 : PS1, Line 273: register "bmc_boot_timeout" = "90"
I just borrowed this value from ocp/tiogapass IIRC, the bootblock wait came much later in developmen […]
Done
File src/mainboard/purism/librem_l1um_v2/ramstage.c:
https://review.coreboot.org/c/coreboot/+/75090/comment/1bdff424_14827fc1 : PS1, Line 30: BIOS_INFO
Ack
Done