[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions

[Cliff Huang (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Felix Held, Hannah Williams, Jamie Ryu, Subrata Banik.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )

Change subject: soc/intel/common/block/pmc: Add GPE1 functions
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Patch Set 11:

(1 comment)

File src/soc/intel/common/block/include/intelblocks/pmclib.h:

https://review.coreboot.org/c/coreboot/+/84104/comment/762b1e16_f57edbf2?usp... :
PS11, Line 241: gpe0_mask
> > shouldn't this be gpe1_mask? same below […]

it is gpe0_mask indeed, as all GPE1 events are finer granularity of some GPE0 events, which included TCSS/non-TCSS PME_B0, hot plug, PCIe events. For instance, if GPE0 PME_EN is disabled, the [internal device]_PME_EN bits will also needs to be disabled. Same thing apply to hot plug and PCIe events. There is no additional types of event added in GPE1. The purpose of GPE1 events is for performance matter. Instead of waking up all device and finding out which one is the event source. GPE1 events is checked directly.