Julian Schroeder has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56188 )
Change subject: soc/amd/cezanne: ACPI CPPC support for AMD ......................................................................
soc/amd/cezanne: ACPI CPPC support for AMD
This leverages the existing CPPC support and adds a cppc init for AMD/Cezanne.
Signed-off-by: Julian Schroeder julianmarcusschroeder@gmail.com Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/acpi.c A src/soc/amd/cezanne/cppc.c A src/soc/amd/cezanne/cppc.h A src/soc/amd/cezanne/cppc_init.c 5 files changed, 223 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56188/1
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index fa38cc3..022f7cc 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -32,6 +32,9 @@
ramstage-y += i2c.c ramstage-y += acpi.c +ramstage-y += cppc_init.c +ramstage-y += cppc.c + ramstage-y += agesa_acpi.c ramstage-y += chip.c ramstage-y += cpu.c diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 6e2ae9c..a130e1d 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -19,6 +19,7 @@ #include <soc/msr.h> #include <types.h> #include "chip.h" +#include "cppc.h"
unsigned long acpi_fill_madt(unsigned long current) { @@ -358,6 +359,8 @@ acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, CSD_HW_ALL, 0);
+ generate_cppc_entries(cpu); + acpigen_pop_len(); }
diff --git a/src/soc/amd/cezanne/cppc.c b/src/soc/amd/cezanne/cppc.c new file mode 100644 index 0000000..df2b6df --- /dev/null +++ b/src/soc/amd/cezanne/cppc.c @@ -0,0 +1,17 @@ +#include <acpi/acpi_pm.h> +#include <acpi/acpigen.h> +#include <arch/cpu.h> +#include "cppc.h" + +void generate_cppc_entries(int core_id) +{ + /* Generate GCPC package in first logical core */ + if (core_id == 0) { + struct cppc_config cppc_config; + cpu_init_cppc_config(&cppc_config, CPPC_VERSION_3); + acpigen_write_CPPC_package(&cppc_config); + } + + /* Write _CPC entry for each logical core */ + acpigen_write_CPPC_method(); +} diff --git a/src/soc/amd/cezanne/cppc.h b/src/soc/amd/cezanne/cppc.h new file mode 100644 index 0000000..43e6fda --- /dev/null +++ b/src/soc/amd/cezanne/cppc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _CPU_AMD_COMMON_H +#define _CPU_AMD_COMMON_H + +#include <types.h> + +struct cppc_config; +void cpu_init_cppc_config(struct cppc_config *config, u32 version); +void generate_cppc_entries(int core_id); + +#endif diff --git a/src/soc/amd/cezanne/cppc_init.c b/src/soc/amd/cezanne/cppc_init.c new file mode 100644 index 0000000..53aa12f --- /dev/null +++ b/src/soc/amd/cezanne/cppc_init.c @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <cpu/x86/msr.h> +#include "cppc.h" + +/* + * version 2 is expected to be the typical use case. + * For now this function 'punts' on version 3 and just + * populates the additional fields with 'unsupported'. + */ +void cpu_init_cppc_config(struct cppc_config *config, u32 version) +{ + acpi_addr_t msr = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 8, + .bit_offset = 0, + .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, //4 + .addrl = 0, + .addrh = 0, + }; + static const acpi_addr_t unsupported = { + .space_id = ACPI_ADDRESS_SPACE_MEMORY, + .bit_width = 0, + .bit_offset = 0, + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, + .addrl = 0, + .addrh = 0, + }; + + config->version = version; + + msr.addrl = 0xc00102b0; + msr.bit_offset = 24; + + /* + * Highest Performance: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x771, 0x04,)}, + */ + config->regs[CPPC_HIGHEST_PERF] = msr; + + /* + * Lowest Nonlinear Performance -> Most Efficient Performance: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)}, + */ + msr.bit_offset = 8; + config->regs[CPPC_LOWEST_NONL_PERF] = msr; + + /* + * Lowest Performance: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x771, 0x04,)}, + */ + msr.bit_offset = 0; + config->regs[CPPC_LOWEST_PERF] = msr; + + /* + * Guaranteed Performance Register: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)}, + */ + config->regs[CPPC_GUARANTEED_PERF] = unsupported; + + + /* + * Nominal Performance -> Maximum Non-Turbo Ratio: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)}, + */ + msr.addrl = 0xc00102b0; + msr.bit_offset = 16; + config->regs[CPPC_NOMINAL_PERF] = msr; + + + /* + * Desired Performance Register: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x774, 0x04,)}, + */ + msr.addrl = 0xc00102b3; + msr.bit_offset = 16; + config->regs[CPPC_DESIRED_PERF] = msr; + + /* + * Minimum Performance Register: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x774, 0x04,)}, + */ + msr.bit_offset = 8; + config->regs[CPPC_MIN_PERF] = msr; + + /* + * Maximum Performance Register: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x774, 0x04,)}, + */ + msr.bit_offset = 0; + config->regs[CPPC_MAX_PERF] = msr; + + /* + * Performance Reduction Tolerance Register: + * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, + */ + config->regs[CPPC_PERF_REDUCE_TOLERANCE] = unsupported; + + /* + * Time Window Register: + * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, + */ + config->regs[CPPC_TIME_WINDOW] = unsupported; + + /* + * Counter Wraparound Time: + * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, + */ + config->regs[CPPC_COUNTER_WRAP] = unsupported; + + /* + * Reference Performance Counter Register: + * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E7, 0x04,)}, + */ + msr.addrl = 0xe7; + msr.bit_width = 64; + msr.bit_offset = 0; + config->regs[CPPC_REF_PERF_COUNTER] = msr; + + + /* + * Delivered Performance Counter Register: + * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E8, 0x04,)}, + */ + msr.addrl = 0xe8; + config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr; + + + /* + * Performance Limited Register: + * ResourceTemplate(){Register(FFixedHW, 0x01, 0x02, 0x777, 0x04,)}, + */ + msr.bit_width = 1; + msr.addrl = 0xc00102b4; + msr.bit_offset = 1; + config->regs[CPPC_PERF_LIMITED] = msr; + + + /* + * CPPC Enable Register: + * ResourceTemplate(){Register(FFixedHW, 0x01, 0x00, 0x770, 0x04,)}, + */ + msr.addrl = 0xc00102b1; + msr.bit_offset = 0; + config->regs[CPPC_ENABLE] = msr; + + if (version >= 2) { + /* Autonomous Selection Enable is populated below */ + + /* + * Autonomous Activity Window Register + * ResourceTemplate(){Register(FFixedHW, 0x0a, 0x20, 0x774, 0x04,)}, + */ + config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = unsupported; + + /* + * Autonomous Energy Performance Preference Register + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x774, 0x04,)}, + */ + msr.addrl = 0xc00102b1; + msr.bit_width = 8; + msr.bit_offset = 24; + config->regs[CPPC_PERF_PREF] = msr; + + /* Reference Performance */ + config->regs[CPPC_REF_PERF] = unsupported; + + if (version >= 3) { + /* Lowest Frequency */ + config->regs[CPPC_LOWEST_FREQ] = unsupported; + /* Nominal Frequency */ + config->regs[CPPC_NOMINAL_FREQ] = unsupported; + } + + /* + * Autonomous Selection Enable = 1 + * This field is actually the first addition in version 2 but + * it's so unlike the others I'm populating it last. + */ + msr.space_id = ACPI_ADDRESS_SPACE_MEMORY; + msr.bit_width = 32; + msr.bit_offset = 0; + msr.access_size = ACPI_ACCESS_SIZE_UNDEFINED; + msr.addrl = 1; + config->regs[CPPC_AUTO_SELECT] = unsupported; + } +}