[coreboot-gerrit] Change in coreboot[master]: mb/google/var/kano: Add gpios to lock

[EricR Lai (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61673 )

Change subject: mb/google/var/kano: Add gpios to lock
......................................................................

mb/google/var/kano: Add gpios to lock

Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.

BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
kano boots successfully to kernel.

Signed-off-by: Eric Lai 
Change-Id: I1d8c003b19381e6a76aff8c844546694c5710e53
---
M src/mainboard/google/brya/variants/kano/gpio.c
1 file changed, 8 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/61673/1

diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c
index 57975f7..8ef3c39 100644
--- a/src/mainboard/google/brya/variants/kano/gpio.c
+++ b/src/mainboard/google/brya/variants/kano/gpio.c
@@ -27,7 +27,7 @@
    PAD_NC(GPP_A22, NONE),

/* D3  : ISH_GP3 ==> NC */
-	PAD_NC(GPP_D3, NONE),
+	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
    /* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
    PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
    /* D6  : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */
@@ -37,11 +37,11 @@
    /* D8  : SRCCLKREQ3# ==> NC */
    PAD_NC(GPP_D8, NONE),
    /* D16 : ISH_UART0_CTS# ==> PEN_PWR_EN */
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG),
    /* D17  : UART1_RXD ==> APU_PEN_DETECT_ODL */
-	PAD_CFG_GPI_SCI(GPP_D17, NONE, DEEP, EDGE_SINGLE, NONE),
+	PAD_CFG_GPI_SCI_LOCK(GPP_D17, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG),
    /* D18 : UART1_TXD ==> NC */
-	PAD_NC(GPP_D18, NONE),
+	PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),

/* E0  : SATAXPCIE0 ==> NC */
    PAD_NC(GPP_E0, NONE),
@@ -50,9 +50,9 @@
    /* E7  : PROC_GP1 ==> NC */
    PAD_NC(GPP_E7, NONE),
    /* E10 : THC0_SPI1_CS# ==> NC */
-	PAD_NC(GPP_E10, NONE),
+	PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
    /* E17 : THC0_SPI1_INT# ==> NC */
-	PAD_NC(GPP_E17, NONE),
+	PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
    /* E22 : DDPA_CTRLCLK ==> NC */
    PAD_NC(GPP_E22, NONE),
    /* E23 : DDPA_CTRLDATA ==> NC */
@@ -72,9 +72,9 @@
    /* H9  : I2C4_SCL ==> NC */
    PAD_NC(GPP_H9, NONE),
    /* H12 : I2C7_SDA ==> NC */
-	PAD_NC(GPP_H12, NONE),
+	PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
    /* H13 : I2C7_SCL ==> NC */
-	PAD_NC(GPP_H13, NONE),
+	PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
    /* H19 : SRCCLKREQ4# ==> NC */
    PAD_NC(GPP_H19, NONE),
    /* H20 : IMGCLKOUT1 ==> NC */