Varshit Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80415?usp=email )
Change subject: soc/amd/glinda: Use gpp_clk_setup_common function ......................................................................
soc/amd/glinda: Use gpp_clk_setup_common function
In follow up to CB:80285 use gpp_clk_setup_common for glinda as well.
Change-Id: Id66d1b7f0d8ec9a7cbd378ad6ad7d68eeab531f0 Signed-off-by: Varshit Pandya pandyavarshit@gmail.com --- M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/chip.h M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/include/soc/southbridge.h 4 files changed, 7 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/80415/1
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index a042ea2..dc5abc7 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -46,6 +46,7 @@ select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_GPP_CLK select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct @@ -76,6 +77,7 @@ select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 diff --git a/src/soc/amd/glinda/chip.h b/src/soc/amd/glinda/chip.h index d33261f..085bac5 100644 --- a/src/soc/amd/glinda/chip.h +++ b/src/soc/amd/glinda/chip.h @@ -7,6 +7,7 @@
#include <amdblocks/chip.h> #include <amdblocks/i2c.h> +#include <amdblocks/pci_clk_req.h> #include <gpio.h> #include <soc/i2c.h> #include <soc/southbridge.h> @@ -92,11 +93,7 @@
/* The array index is the general purpose PCIe clock output number. Values in here aren't the values written to the register to have the default to be always on. */ - enum { - GPP_CLK_ON, /* GPP clock always on; default */ - GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ - GPP_CLK_OFF, /* GPP clk off */ - } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; + enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
/* performance policy for the PCIe links: power consumption vs. link speed */ enum { diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index 93597c9..2218ce3 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -6,6 +6,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> +#include <amdblocks/pci_clk_req.h> #include <amdblocks/reset.h> #include <amdblocks/smi.h> #include <assert.h> @@ -130,45 +131,8 @@ /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { - const struct soc_amd_glinda_config *cfg = config_of_soc(); - - /* look-up table to be able to iterate over the PCIe clock output settings */ - const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { - GPP_CLK0_REQ_SHIFT, - GPP_CLK1_REQ_SHIFT, - GPP_CLK2_REQ_SHIFT, - GPP_CLK3_REQ_SHIFT, - GPP_CLK4_REQ_SHIFT, - GPP_CLK5_REQ_SHIFT, - GPP_CLK6_REQ_SHIFT, - }; - - uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); - - for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { - gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); - /* - * The remapping of values is done so that the default of the enum used for the - * devicetree settings is the clock being enabled, so that a missing devicetree - * configuration for this will result in an always active clock and not an - * inactive PCIe clock output. Only the configuration for the clock outputs - * available on the package is provided via the devicetree; the rest is - * switched off unconditionally. - */ - switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) { - case GPP_CLK_REQ: - gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); - break; - case GPP_CLK_OFF: - gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]); - break; - case GPP_CLK_ON: - default: - gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]); - } - } - - misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); + struct soc_amd_glinda_config *cfg = config_of_soc(); + gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config)); }
static void cgpll_clock_gate_init(void) diff --git a/src/soc/amd/glinda/include/soc/southbridge.h b/src/soc/amd/glinda/include/soc/southbridge.h index 32945e8..9cd835b 100644 --- a/src/soc/amd/glinda/include/soc/southbridge.h +++ b/src/soc/amd/glinda/include/soc/southbridge.h @@ -87,20 +87,7 @@ #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
/* FCH MISC Registers 0xfed80e00 */ -#define GPP_CLK_CNTRL 0x00 -#define GPP_CLK0_REQ_SHIFT 0 -#define GPP_CLK1_REQ_SHIFT 2 -#define GPP_CLK4_REQ_SHIFT 4 -#define GPP_CLK2_REQ_SHIFT 6 -#define GPP_CLK3_REQ_SHIFT 8 -#define GPP_CLK5_REQ_SHIFT 10 -#define GPP_CLK6_REQ_SHIFT 12 -#define GPP_CLK_OUTPUT_COUNT 7 #define GPP_CLK_OUTPUT_AVAILABLE 4 -#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) -#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) -#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) -#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift))
#define MISC_CLKGATEDCNTL 0x2c #define ALINKCLK_GATEOFFEN BIT(16)