[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Select number of I/O for ADL-N

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik, Krishna P Bhat D, Usha P, Patrick Rudolph.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59752 )

Change subject: soc/intel/alderlake: Select number of I/O for ADL-N
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Patch Set 1:

(1 comment)

File src/soc/intel/alderlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/59752/comment/f985af61_46036137 
PS1, Line 177: SOC_INTEL_ALDERLAKE_PCH_N
ADL-N support max of 5 PCIE ports (upto 9 PCIe lanes). Please check once.