Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76185?usp=email )
Change subject: {mb/intel/ac, soc/intel/xeon_sp/spr}: Let soc configure IIO UPDs from mainboard ......................................................................
{mb/intel/ac, soc/intel/xeon_sp/spr}: Let soc configure IIO UPDs from mainboard
Attempt to deduplicate mainboard mainboard_config_iio since there are a few SPR-SP mainboards now.
Each mainboard needs to have a "include/sprsp_mb_iio.h" which defines its mb_iio_table and mb_iio_bifur for IIO configurations, and soc common code can configure IIO UPD from them.
This change removes initializing below UPD default non zero values, so mainboard needs to make sure they are defined in its mb_iio_table: PciePortConfig[socket].PcieMaxPayload[port] = 0x7; /* Auto */ PciePortConfig[socket].DfxDnTxPresetGen3[port] = 0xff; /* Auto */
Not thoroughly tested yet. Need to modfiy and verify other SPR mainboards, and use DISPLAY_UPD_IIO_DATA to compare the results.
Change-Id: I72d74241fcad4c85a95f6d14587418f544caadd9 Signed-off-by: Johnny Lin johnny_lin@wiwynn.com --- R src/mainboard/intel/archercity_crb/include/sprsp_mb_iio.h M src/mainboard/intel/archercity_crb/romstage.c M src/soc/intel/xeon_sp/spr/Makefile.inc M src/soc/intel/xeon_sp/spr/romstage.c 4 files changed, 79 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/76185/1
diff --git a/src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h b/src/mainboard/intel/archercity_crb/include/sprsp_mb_iio.h similarity index 87% rename from src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h rename to src/mainboard/intel/archercity_crb/include/sprsp_mb_iio.h index 2dcf6c9..e10be76 100644 --- a/src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h +++ b/src/mainboard/intel/archercity_crb/include/sprsp_mb_iio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef _SPRSP_AC_IIO_H_ -#define _SPRSP_AC_IIO_H_ +#ifndef _SPRSP_MB_IIO_H_ +#define _SPRSP_MB_IIO_H_
#include <defs_iio.h>
@@ -35,10 +35,13 @@ .DfxDnTxPresetGen3 = 0xFF \ }
+#define IIO_PORT_SETTINGS (1 + 5 * 8) + /* * Standard ArcherCity IIO PCIe Port Table */ -static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt0[] = { +static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY mb_iio_table[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = { + { /* DMI port: array index 0 */ CFG_UPD_PCIE_PORT(0, 0, 0), /* IOU0 (PE0): array index 1 ~ 8 */ @@ -86,10 +89,8 @@ CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(0, 1, 39), /* 59:07.0 */ CFG_UPD_PCIE_PORT(1, 0, 0), - /* ArcherCity doesn't use IOU5 ~ IOU6. */ -}; - -static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt1[] = { + }, + { /* DMI port: array index 0 */ CFG_UPD_PCIE_PORT(1, 0, 0), /* IOU0 (PE0): array index 1 ~ 8 */ @@ -137,6 +138,23 @@ CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(0, 1, 39), /* d7:07.0 */ CFG_UPD_PCIE_PORT(1, 0, 0), - /* ArcherCity doesn't use IOU5 ~ IOU6. */ + }, }; -#endif /* _SPRSP_CL_IIO_H_ */ + +static const UINT8 mb_iio_bifur[CONFIG_MAX_SOCKET][5] = { + { + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_x4x4x4x4, + IIO_BIFURCATE_x4x4x4x4, + }, + { + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_x4x4x4x4, + IIO_BIFURCATE_x4x4x4x4, + }, +}; +#endif /* _SPRSP_MB_IIO_H_ */ diff --git a/src/mainboard/intel/archercity_crb/romstage.c b/src/mainboard/intel/archercity_crb/romstage.c index 582fa50..340af0d 100644 --- a/src/mainboard/intel/archercity_crb/romstage.c +++ b/src/mainboard/intel/archercity_crb/romstage.c @@ -7,7 +7,7 @@ #include <soc/romstage.h> #include <defs_cxl.h> #include <defs_iio.h> -#include <sprsp_ac_iio.h> +#include <sprsp_mb_iio.h>
void mainboard_ewl_check(void) { @@ -16,59 +16,6 @@
static void mainboard_config_iio(FSPM_UPD *mupd) { - int port; - - UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = - (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr; - - /* Socket0: Array ac_iio_pci_port_skt0 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ - for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt0); port++) { - PciePortConfig[0].SLOTIMP[port] = ac_iio_pci_port_skt0[port].SLOTIMP; - PciePortConfig[0].SLOTPSP[port] = ac_iio_pci_port_skt0[port].SLOTPSP; - PciePortConfig[0].PciePortEnable[port] = ac_iio_pci_port_skt0[port].PciePortEnable; - PciePortConfig[0].PEXPHIDE[port] = ac_iio_pci_port_skt0[port].PEXPHIDE; - PciePortConfig[0].PcieMaxPayload[port] = ac_iio_pci_port_skt0[port].PcieMaxPayload; - PciePortConfig[0].PciePortLinkSpeed[port] = ac_iio_pci_port_skt0[port].PciePortLinkSpeed; - PciePortConfig[0].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt0[port].DfxDnTxPresetGen3; - } - /* Socket0: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ - for (port = ARRAY_SIZE(ac_iio_pci_port_skt0); port < MAX_IIO_PORTS_PER_SOCKET; port++) { - PciePortConfig[0].PEXPHIDE[port] = 1; - PciePortConfig[0].HidePEXPMenu[port] = 1; - } - PciePortConfig[0].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16; - PciePortConfig[0].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16; - PciePortConfig[0].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16; - PciePortConfig[0].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4; - PciePortConfig[0].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4; - - PciePortConfig[0].PcieGlobalAspm = 0x1; - PciePortConfig[0].PcieMaxReadRequestSize = 0x5; - - /* Socket1: Array ac_iio_pci_port_skt1 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ - for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt1); port++) { - PciePortConfig[1].SLOTIMP[port] = ac_iio_pci_port_skt1[port].SLOTIMP; - PciePortConfig[1].SLOTPSP[port] = ac_iio_pci_port_skt1[port].SLOTPSP; - PciePortConfig[1].PciePortEnable[port] = ac_iio_pci_port_skt1[port].PciePortEnable; - PciePortConfig[1].PEXPHIDE[port] = ac_iio_pci_port_skt1[port].PEXPHIDE; - PciePortConfig[1].PcieMaxPayload[port] = ac_iio_pci_port_skt1[port].PcieMaxPayload; - PciePortConfig[1].PciePortLinkSpeed[port] = ac_iio_pci_port_skt1[port].PciePortLinkSpeed; - PciePortConfig[1].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt1[port].DfxDnTxPresetGen3; - } - /* Socket1: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ - for (port = ARRAY_SIZE(ac_iio_pci_port_skt1); port < MAX_IIO_PORTS_PER_SOCKET; port++) { - PciePortConfig[1].PEXPHIDE[port] = 1; - PciePortConfig[1].HidePEXPMenu[port] = 1; - } - PciePortConfig[1].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16; - PciePortConfig[1].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16; - PciePortConfig[1].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16; - PciePortConfig[1].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4; - PciePortConfig[1].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4; - - PciePortConfig[1].PcieGlobalAspm = 0x1; - PciePortConfig[1].PcieMaxReadRequestSize = 0x5; - /* If CONFIG(OCP_VPD) is not enabled or CXL is explicitly disabled, don't enable CXL */ if (!CONFIG(OCP_VPD) || get_cxl_mode_from_vpd() == CXL_DISABLED) { printk(BIOS_DEBUG, "Don't enable CXL via VPD %s\n", CXL_MODE); diff --git a/src/soc/intel/xeon_sp/spr/Makefile.inc b/src/soc/intel/xeon_sp/spr/Makefile.inc index 3e4f9cd..0703542 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.inc +++ b/src/soc/intel/xeon_sp/spr/Makefile.inc @@ -17,6 +17,7 @@ ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c smm-$(CONFIG_HAVE_SMI_HANDLER) += soc_smihandler_util.c -CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr +CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr \ + -I$(src)/mainboard/$(MAINBOARDDIR)/include
endif ## CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 8004730..60b21ce 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -19,11 +19,11 @@ #include <string.h> #include <soc/soc_util.h> #include <soc/ddr.h> +#include <sprsp_mb_iio.h>
#include "chip.h"
/* Initialize to all zero first */ -static UPD_IIO_PCIE_PORT_CONFIG spr_iio_bifur_table[MAX_SOCKET]; static UINT8 deemphasis_list[MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET];
void __weak mainboard_memory_init_params(FSPM_UPD *mupd) @@ -113,22 +113,55 @@ } }
-/* Initialize non-zero default UPD values for IIO */ -static void initialize_iio_upd(FSPM_UPD *mupd) +static void soc_config_iio_from_mb(FSPM_UPD *mupd) { - unsigned int port, socket; + UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig; + int port, socket;
- mupd->FspmConfig.IioPcieConfigTablePtr = (UINT32)spr_iio_bifur_table; - mupd->FspmConfig.IioPcieConfigTableNumber = MAX_SOCKET; - UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = - (UPD_IIO_PCIE_PORT_CONFIG *)spr_iio_bifur_table; + PciePortConfig = + (UPD_IIO_PCIE_PORT_CONFIG *)(UINTN)mupd->FspmConfig.IioPcieConfigTablePtr; + mupd->FspmConfig.IioPcieConfigTableNumber = CONFIG_MAX_SOCKET; /* Set by mainboard */
- /* Initialize non-zero default UPD values */ - for (socket = 0; socket < MAX_SOCKET; socket++) { - for (port = 0; port < MAX_IIO_PORTS_PER_SOCKET; port++) { - PciePortConfig[socket].PcieMaxPayload[port] = 0x7; /* Auto */ - PciePortConfig[socket].DfxDnTxPresetGen3[port] = 0xff; /* Auto */ + for (socket = 0; socket < CONFIG_MAX_SOCKET; socket++) { + + /* Only configures DMI, IOU0 ~ IOU4, the rest will be + * left zero */ + for (port = 0; port < ARRAY_SIZE(mb_iio_table[socket]); port++) { + const UPD_IIO_PCIE_PORT_CONFIG_ENTRY *port_cfg = + &mb_iio_table[socket][port]; + PciePortConfig[socket].SLOTIMP[port] = port_cfg->SLOTIMP; + PciePortConfig[socket].SLOTPSP[port] = port_cfg->SLOTPSP; + PciePortConfig[socket].SLOTHPCAP[port] = port_cfg->SLOTHPCAP; + PciePortConfig[socket].SLOTHPSUP[port] = port_cfg->SLOTHPSUP; + PciePortConfig[socket].SLOTSPLS[port] = port_cfg->SLOTSPLS; + PciePortConfig[socket].SLOTSPLV[port] = port_cfg->SLOTSPLV; + PciePortConfig[socket].VppAddress[port] = port_cfg->VppAddress; + PciePortConfig[socket].SLOTPIP[port] = port_cfg->SLOTPIP; + PciePortConfig[socket].SLOTAIP[port] = port_cfg->SLOTAIP; + PciePortConfig[socket].SLOTMRLSP[port] = port_cfg->SLOTMRLSP; + PciePortConfig[socket].SLOTPCP[port] = port_cfg->SLOTPCP; + PciePortConfig[socket].SLOTABP[port] = port_cfg->SLOTABP; + PciePortConfig[socket].VppEnabled[port] = port_cfg->VppEnabled; + PciePortConfig[socket].VppPort[port] = port_cfg->VppPort; + PciePortConfig[socket].MuxAddress[port] = port_cfg->MuxAddress; + PciePortConfig[socket].PciePortEnable[port] = port_cfg->PciePortEnable; + PciePortConfig[socket].PEXPHIDE[port] = port_cfg->PEXPHIDE; + PciePortConfig[socket].PcieHotPlugOnPort[port] = port_cfg->PcieHotPlugOnPort; + PciePortConfig[socket].PcieMaxPayload[port] = port_cfg->PcieMaxPayload; + PciePortConfig[socket].PciePortLinkSpeed[port] = port_cfg->PciePortLinkSpeed; + PciePortConfig[socket].DfxDnTxPresetGen3[port] = port_cfg->DfxDnTxPresetGen3; } + + /* Socket IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ + for (port = ARRAY_SIZE(mb_iio_table[socket]); port < MAX_IIO_PORTS_PER_SOCKET; + port++) { + PciePortConfig[socket].PEXPHIDE[port] = 1; + PciePortConfig[socket].HidePEXPMenu[port] = 1; + } + /* Configure IOU0 ~ IOU4 bifurcation */ + for (port = 0; port < 5; port++) + PciePortConfig[socket].ConfigIOU[port] = mb_iio_bifur[socket][port]; + PciePortConfig[socket].PcieGlobalAspm = 0x1; /* Enable ASPM */ PciePortConfig[socket].PcieMaxReadRequestSize = 0x5; } @@ -136,7 +169,6 @@ mupd->FspmConfig.DeEmphasisPtr = (UINT32)deemphasis_list; mupd->FspmConfig.DeEmphasisNumber = MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET; UINT8 *DeEmphasisConfig = (UINT8 *)deemphasis_list; - for (port = 0; port < MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET; port++) DeEmphasisConfig[port] = 0x1; } @@ -198,7 +230,9 @@ /* Set some common UPDs from VPD, mainboard can still override them if needed */ if (CONFIG(VPD)) config_upd_from_vpd(mupd); - initialize_iio_upd(mupd); + /* soc configures IIO UPD from mainboard defined mb_iio_table and mb_iio_bifur, + mainboard can still furthur overwrite in its mainboard_config_iio. */ + soc_config_iio_from_mb(mupd); mainboard_memory_init_params(mupd);
if (CONFIG(ENABLE_IO_MARGINING)) {