Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31568
Change subject: soc/cavium/cn81xx: Drop VBOOT_RETURN_FROM_VERSTAGE ......................................................................
soc/cavium/cn81xx: Drop VBOOT_RETURN_FROM_VERSTAGE
To support measured boot, drop VBOOT_RETURN_FROM_VERSTAGE. The SoC has enough CAR space to support a separate verstage.
Tested on OpenCellular Elgon.
Change-Id: I18022000f6f05df89d3037896ef627070bfcca06 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/cavium/cn81xx/Kconfig M src/soc/cavium/cn81xx/include/soc/memlayout.ld 2 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31568/1
diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 4bf2e65..9119bcc 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -18,7 +18,6 @@
config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK
config ARM64_BL31_EXTERNAL_FILE diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index 2222617..8412dff 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -33,9 +33,10 @@ TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K) PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) - BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) - VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) - VERSTAGE(BOOTROM_OFFSET + 0x33000, 52K) + BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 32K) + VBOOT2_WORK(BOOTROM_OFFSET + 0x28000, 12K) + VBOOT2_TPM_LOG(BOOTROM_OFFSET + 0x2b000, 2K) + VERSTAGE(BOOTROM_OFFSET + 0x2c000, 78K) ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K)
SRAM_END(BOOTROM_OFFSET + 0x80000)