mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: initial SoC support ......................................................................
sc7180: initial SoC support
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney mturney@codeaurora.org --- A src/soc/qualcomm/sc7180/Kconfig A src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/cbmem.c A src/soc/qualcomm/sc7180/gpio.c A src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/gpio.h A src/soc/qualcomm/sc7180/include/soc/memlayout.ld A src/soc/qualcomm/sc7180/include/soc/mmu.h A src/soc/qualcomm/sc7180/include/soc/symbols.h A src/soc/qualcomm/sc7180/mmu.c A src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7180/soc.c A src/soc/qualcomm/sc7180/spi.c A src/soc/qualcomm/sc7180/timer.c A src/soc/qualcomm/sc7180/uart_bitbang.c 16 files changed, 642 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35494/1
diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig new file mode 100644 index 0000000..70737e9 --- /dev/null +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -0,0 +1,25 @@ + +config SOC_QUALCOMM_SC7180 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + select ARM64_USE_ARCH_TIMER + select SOC_QUALCOMM_COMMON + select HAVE_UART_SPECIAL + select BOOTBLOCK_CONSOLE + +if SOC_QUALCOMM_SC7180 + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc new file mode 100644 index 0000000..a973724 --- /dev/null +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -0,0 +1,47 @@ + +ifeq ($(CONFIG_SOC_QUALCOMM_SC7180),y) + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c +bootblock-y += timer.c +bootblock-y += gpio.c +bootblock-y += spi.c +bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ +verstage-y += timer.c +verstage-y += gpio.c +verstage-y += spi.c +verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += timer.c +romstage-y += gpio.c +romstage-y += ../common/qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c +romstage-y += spi.c +romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += cbmem.c +ramstage-y += timer.c +ramstage-y += gpio.c +ramstage-y += spi.c +ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sc7180/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +################################################################################ + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin + +endif diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c new file mode 100644 index 0000000..b9b8660 --- /dev/null +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void bootblock_soc_init(void) +{ + sc7180_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c new file mode 100644 index 0000000..597e369 --- /dev/null +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)((uintptr_t)4 * GiB); +} diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c new file mode 100644 index 0000000..bb5baf5 --- /dev/null +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <assert.h> +#include <types.h> +#include <gpio.h> + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable) +{ + +} + +void gpio_set(gpio_t gpio, int value) +{ + +} + +int gpio_get(gpio_t gpio) +{ + return 0; +} + +void gpio_input_pulldown(gpio_t gpio) +{ + +} + +void gpio_input_pullup(gpio_t gpio) +{ + +} + +void gpio_input(gpio_t gpio) +{ + +} + +void gpio_output(gpio_t gpio, int value) +{ + +} + +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) +{ + +} + +int gpio_irq_status(gpio_t gpio) +{ + return 0; +} diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h new file mode 100644 index 0000000..93f0481 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ +#define _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ + +#include <stdint.h> + +#endif /* _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h new file mode 100644 index 0000000..170854c --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_GPIO_H_ +#define _SOC_QUALCOMM_SC7180_GPIO_H_ + +#include <types.h> +#include <soc/addressmap.h> + +typedef struct { + u32 addr; +} gpio_t; + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Status */ +#define GPIO_OUTPUT_DISABLE 0 +#define GPIO_OUTPUT_ENABLE 1 + +#define GPIO_FUNC_GPIO 0 + +#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) + +/* TODO: fill this in for Rennell */ +#if 0 +#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ +GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ +GPIO##index##_FUNC_##func1 = 1, \ +GPIO##index##_FUNC_##func2 = 2, \ +GPIO##index##_FUNC_##func3 = 3, \ +GPIO##index##_FUNC_##func4 = 4, \ +GPIO##index##_FUNC_##func5 = 5, \ +GPIO##index##_FUNC_##func6 = 6, \ +GPIO##index##_FUNC_##func7 = 7 + +enum { + PIN(0, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), +}; +#endif + +enum gpio_irq_type { + IRQ_TYPE_LEVEL = 0, + IRQ_TYPE_RISING_EDGE = 1, + IRQ_TYPE_FALLING_EDGE = 2, + IRQ_TYPE_DUAL_EDGE = 3, +}; + +struct tlmm_gpio { + uint32_t cfg; + uint32_t in_out; + uint32_t intr_cfg; + uint32_t intr_status; +}; + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable); +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull); +int gpio_irq_status(gpio_t gpio); + +#endif /* _SOC_QUALCOMM_SC7180_GPIO_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld new file mode 100644 index 0000000..ae00816 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* SYSTEM_IMEM : 0x14680000 - 0x14699000 */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14900000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +SECTIONS +{ + SSRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + REGION(qcsdi, 0x14699000, 52K, 4K) + SSRAM_END(0x146A6000) + + BSRAM_START(0x14800000) + REGION(bsram_reserved1, 0x14800000, 84K, 4K) + BOOTBLOCK(0x14815000, 40K) + PRERAM_CBFS_CACHE(0x1481F000, 70K) + PRERAM_CBMEM_CONSOLE(0x14830800, 32K) + TIMESTAMP(0x14838800, 1K) + REGION(bsram_align1, 0x14838C00, 1K, 1K) + TTB(0x14839000, 56K) + STACK(0x14847000, 16K) + VBOOT2_WORK(0x1484B000, 12K) + DMA_COHERENT(0x1484E000, 8K) + REGION(ddr_training, 0x14850000, 8K, 4K) + REGION(qclib_serial_log, 0x14852000, 4K, 4K) + REGION(ddr_information, 0x14853000, 1K, 1K) + REGION(bsram_unused, 0x14853400, 0x1CC00, 1K) + REGION(dcb, 0x14870000, 16K, 4K) + REGION(pmic, 0x14874000, 44K, 4K) + REGION(limits_cfg, 0x1487F000, 4K, 4K) + REGION(qclib, 0x14880000, 512K, 4K) + BSRAM_END(0x14900000) + + DRAM_START(0x80000000) + REGION(dram_reserved1, 0x80820000, 0x20000, 0x1000) + REGION(dram_reserved, 0x80900000, 0x200000, 0x1000) + /* Various hardware/software subsystems make use of this area */ + BL31(0x85000000, 0x1A800000) + POSTRAM_CBFS_CACHE(0x9F800000, 384K) + RAMSTAGE(0x9F860000, 2M) +} diff --git a/src/soc/qualcomm/sc7180/include/soc/mmu.h b/src/soc/qualcomm/sc7180/include/soc/mmu.h new file mode 100644 index 0000000..735ce17 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/mmu.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_MMU_H_ +#define _SOC_QUALCOMM_SC7180_MMU_H_ + +void sc7180_mmu_init(void); + +#endif /* _SOC_QUALCOMM_SC7180_MMU_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h new file mode 100644 index 0000000..14b779f --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_SYMBOLS_H_ +#define _SOC_QUALCOMM_SC7180_SYMBOLS_H_ + +#include <symbols.h> + +DECLARE_REGION(ssram) +DECLARE_REGION(bsram) +DECLARE_REGION(dram_reserved) +DECLARE_REGION(dram_reserved1) +DECLARE_REGION(el3_stack_canary); +DECLARE_REGION(dcb); +DECLARE_REGION(pmic); +DECLARE_REGION(limits_cfg); + +#endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c new file mode 100644 index 0000000..fd59a5a --- /dev/null +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <symbols.h> +#include <arch/mmu.h> +#include <arch/cache.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +void sc7180_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_RAM); + + mmu_enable(); +} + diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c new file mode 100644 index 0000000..9c05452 --- /dev/null +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <fmap.h> +#include <console/console.h> +#include <soc/symbols.h> +#include <soc/qclib_common.h> + +int qclib_soc_blob_load(void) +{ + size_t size; + ssize_t ssize; + + /* Attempt to load PMICCFG Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); + + /* Attempt to load DCB Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); + + /* Attempt to load Limits Config Blob */ + ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, + REGION_SIZE(limits_cfg)); + if (ssize < 0) + return -1; + qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, + _limits_cfg, ssize, 0); + + return 0; +} diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c new file mode 100644 index 0000000..4fc5b30 --- /dev/null +++ b/src/soc/qualcomm/sc7180/soc.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <symbols.h> +#include <device/device.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, + REGION_SIZE(dram_reserved) / KiB); + reserved_ram_resource(dev, 2, (uintptr_t)_dram_reserved1 / KiB, + REGION_SIZE(dram_reserved1) / KiB); + + + +} + +static void soc_init(struct device *dev) +{ + +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sc7180_ops = { + CHIP_NAME("SOC Qualcomm SC7180") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c new file mode 100644 index 0000000..5abb81a --- /dev/null +++ b/src/soc/qualcomm/sc7180/spi.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static const struct spi_ctrlr spi_ctrlr; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sc7180/timer.c b/src/soc/qualcomm/sc7180/timer.c new file mode 100644 index 0000000..5b78c1d --- /dev/null +++ b/src/soc/qualcomm/sc7180/timer.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <arch/lib_helpers.h> +#include <commonlib/helpers.h> + +void init_timer(void) +{ + raw_write_cntfrq_el0(19200*KHz); +} diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c new file mode 100644 index 0000000..813be89 --- /dev/null +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * Copyright 2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> +#include <gpio.h> +#include <types.h> + +#if 0 +#define UART_TX_PIN GPIO(4) +#else +#include <boot/coreboot_tables.h> +gpio_t uart_gpio = { 0 }; +#define UART_TX_PIN uart_gpio + +void uart_fill_lb(void *data) +{ + +} +#endif + + +static void set_tx(int line_state) +{ + gpio_set(UART_TX_PIN, line_state); +} + +void uart_init(int idx) +{ + gpio_output(UART_TX_PIN, 1); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + uart_bitbang_tx_byte(data, set_tx); +} + +void uart_tx_flush(int idx) +{ + /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ +} + +unsigned char uart_rx_byte(int idx) +{ + return 0; /* not implemented */ +}