[coreboot-gerrit] [S] Change in coreboot[main]: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD

[Jarried Lin (Code Review)]

Attention is currently required from: Hope Wang.

Hello Hope Wang,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/85751?usp=email

to review the following change.

Change subject: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD
......................................................................

soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD

Configure the SCL and SDA of the SPMI-P to Pull-Down mode on MT8196 SoC,
to fix spmi clk calibration failure.

TEST=Build pass
BUG=b:361174333

Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f
Signed-off-by: Hope Wang 
---
M src/soc/mediatek/mt8196/include/soc/pmif.h
M src/soc/mediatek/mt8196/pmif_spmi.c
2 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/85751/1

diff --git a/src/soc/mediatek/mt8196/include/soc/pmif.h b/src/soc/mediatek/mt8196/include/soc/pmif.h
index a114dc6..189ee2a 100644
--- a/src/soc/mediatek/mt8196/include/soc/pmif.h
+++ b/src/soc/mediatek/mt8196/include/soc/pmif.h
@@ -4,6 +4,7 @@
 #define __MT8196_SOC_PMIF_H__

#include <device/mmio.h>
+#include <soc/addressmap.h>
 #include <soc/pmif_common.h>
 #include <types.h>

@@ -138,6 +139,10 @@
 #define FREQ_METER_VLP_AD_OSC_CK	59
 #define PMIF_USE_FIX_26M_CLK            0

+#define SPMI_SCL_P_PD_ADDR	(IOCFG_LM2_BASE+0x80)
+#define SPMI_SCL_P_PD_OFFSET	4
+#define SPMI_SDA_P_PD_OFFSET	5
+
 /* calibation tolerance rate, unit: 0.1% */
 enum {
    CAL_TOL_RATE = 40,
diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c
index 91f9038..aea0730 100644
--- a/src/soc/mediatek/mt8196/pmif_spmi.c
+++ b/src/soc/mediatek/mt8196/pmif_spmi.c
@@ -174,6 +174,13 @@
 {
    u32 rdata = 0;

+	if (dev->slvid == SPMI_SLAVE_6) {
+		setbits32p(SPMI_SCL_P_PD_ADDR,
+			   BIT(SPMI_SCL_P_PD_OFFSET) | BIT(SPMI_SDA_P_PD_OFFSET));
+		printk(BIOS_INFO, "%s, Set SoC PD for SPMI-P SCL/SDA, [0x%x] = 0x%x\n",
+		       __func__, SPMI_SCL_P_PD_ADDR, read32p(SPMI_SCL_P_PD_ADDR));
+	}
+
    arb->read(arb, dev->slvid, dev->hwcid_addr, &rdata);
    if ((rdata & dev->hwcid_mask) != (dev->hwcid_val & dev->hwcid_mask)) {
    	printk(BIOS_WARNING, "%s next, slvid:%d rdata = 0x%x\n",